JPS6239778B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a software interrupt level expansion method, and more particularly to a software interrupt level expansion method in a processor that executes software interrupt instructions.

This type of software interrupt instruction is used not only when a processor is executing a processing program to transfer processing to an execution management program, but also when calling various subroutine programs.

FIG. 1 is a diagram showing an example of a conventional software interrupt instruction execution method in this type of processor. In Figure 1, software interrupt instruction SWI
Prior to executing , the processor OPU executes an instruction LDX that stores a level value i (i is 1 to N, hereinafter the same) indicating the type of processing to be executed in the built-in index register X. In such a state, the software interrupt instruction SWI is stored in memory.
The processor CPU that has read from MEM saves the contents of built-in registers to memory MEM as is well known, and then sequentially sends specific addresses AX and AX+1 to address buses AB0 to AB15, The lower 8 bits AY (L) and upper 8 bits AY (H) of a specific address AY stored in advance in the data bus
It is read out sequentially via DB0 to DB7 and stored in the program counter PC as address AY. Next, the processor OPU transfers the address AY stored in the program counter PC from the address bus AB0 to
AB15 and starts execution of the software interrupt management program P0. During the execution process of the management program P0, the processor CPU uses the level value i stored in the index register in advance.
The starting address Ai of the processing program Pi corresponding to
and sends it to address buses AB0 to AB15 to start execution of the processing program Pi.

As is clear from the above explanation, according to the conventional software interrupt instruction execution method, the processor
Before executing the desired processing program Pi corresponding to the level value i, the CPU must first execute the management program P0 and select the processing program Pi to be executed next, in order to select and execute various processes. First, it increases the execution time of the software interrupt instruction SWI.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the conventional software interrupt instruction execution method as described above, and to shorten the time required for a processor to execute a software interrupt instruction that involves various processing.

The purpose of this is that in a processor that executes a software interrupt instruction, when the processor detects a predetermined address to be sent to the address bus, it simultaneously creates a register that stores data to be sent to the data bus, and a register that stores the data stored in the register. a conversion means for creating a corresponding address; and when the processor detects a predetermined address to be sent to the address bus when executing the software interrupt instruction, the processor sends the address created by the conversion means to the data bus. This can be achieved by arranging means to do this.

An embodiment of the present invention will be described below with reference to FIG. FIG. 2 is a diagram showing a software interrupt instruction execution method according to an embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures. In FIG. 2, a level register LVR, a conversion circuit TRL, and various gate circuits G1 to G4 are provided outside the processor CPU, and are connected to the processor CPU via address buses AB0 to AB15 or data buses DB0 to DB7. . Before executing the software interrupt instruction SWI, the processor CPU first executes the instruction LDAA#LVi,
Accumulator with built-in level value #LVi that indicates the type of processing to be executed by software interrupt
Accumulates in AA. Next, the processor CPU
Executes STAA LVR and transfers the address AL assigned to the level register LVR to address buses AB0 to AB1.
5, and also sends the level value #LVi stored in the accumulator AA. Gate G3 detects the address AL sent to address buses AB0 to AB15 and turns gate G1 into a conductive state. As a result, the level value #LVi sent to the data buses DB0 to DB7 is stored in the level register.
Accumulated in LVR. On the other hand, the conversion circuit TLR receives the level value #LVi being stored from the level register LVR, and converts it to the start address Ai where the processing program Pi corresponding to the level value #LVi is stored. In such a state, a software interrupt instruction
Processor CPU that read SWI from memory MEM
is the same as in Figure 1, the address bus AB
First, a specific address AX is sent from 0 to AB15. Gate G4 is connected to address buses AB1 to AB15
The address AX (excluding the least significant bit) sent to the address AX is detected, and the gate G2 is made conductive. Also, the conversion circuit TLR receives the lowest bit 0 of the address AX sent to the address bus AB0.
sends the lower 8 bits Ai(L) of the start address Ai to the data buses DB0 to DB7 via the gate G2. The processor CPU receives the lower 8 bits Ai(L) of the start address Ai via the data buses DB0 to DB7, and stores it in the lower 8 bits of the program counter PC. Next is the processor CPU
sends a specific address AX+1 to address buses AB0 to AB15. Gate G4 makes gate G2 conductive in the same manner as described above. Further, the conversion circuit TLR that receives the least significant bit 1 of the address AX+1 sent to the address bus AB0 sends the upper 8 bits Ai(H) of the start address Ai to the data buses DB0 to DB7 via the gate G2. The processor CPU receives the upper 8 bits Ai(H) of the start address Ai via the data buses DB0 to DB7, and stores it in the upper 8 bits of the program counter PC. As described above, the start address Ai of the processing program Pi is stored in the program counter PC of the processor CPU. From now on, the processor CPU
executes the processing program Pi in the same way as in FIG.

As is clear from the above explanation, according to this embodiment, the processor CPU receives software interrupt instructions.
When executing SWI, specific addresses AX and AX
When +1 is sent to the address buses AB0 to AB15, the start address Ai of the desired processing program Pi can be immediately received from the data buses DB0 to DB7, and as shown in FIG.
The process of reading address AY from MEM and executing management program P0 is completely unnecessary.

Note that FIG. 2 is only one embodiment of the present invention, and for example, the address buses AB0 to AB15 and the data buses DB0 to DB7 each have a configuration of 16
The number is not limited to 8 and 8, and the effects of the present invention do not change even if the number is set to any other arbitrary number. In addition, along with this, data buses DB0 to DB7 are connected from the conversion circuit TLR to
The method of sending the address Ai is not limited to the one shown in the figure, and various modifications may be considered, but the effects of the present invention remain the same in either case.

As described above, according to the present invention, a processor that executes a software interrupt instruction can immediately obtain the start address of a processing program to execute a desired process, and the execution time of the software interrupt instruction is shortened. be done.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a conventional software interrupt instruction execution method, and FIG. 2 is a diagram showing a software interrupt instruction execution method according to an embodiment of the present invention. In the figure, CPU is a processor, MEM is a memory, AB0 to AB15 are address buses, DB0 to DB7 are data buses, X is an index register, PC is a program counter, AA is an accumulator, AX, AX+1, AY(L), AY( H),AY,A1
AN to AN and AL are addresses, P0 is a management program, P1 to PN are processing programs, LVR is a level register, TLR is a conversion circuit, G1 to G
4 is a gate, #LV is a level value, R is a signal indicating that the processor reads data, and W is a signal indicating that the processor also writes data.

Claims (1)

[Claims] 1 In a processor that executes a software interrupt instruction, when the processor detects a predetermined address to be sent to the address bus, it simultaneously creates a register that stores data to be sent to the data bus, and an address corresponding to the data stored in the register. and means for sending the address created by the converting means to the data bus when the processor detects a predetermined address to be sent to the address bus when executing the software interrupt instruction. A software interrupt level expansion method characterized by arranging.