JPH03104237U

JPH03104237U -

Info

Publication number: JPH03104237U
Application number: JP1358890U
Authority: JP
Priority date: 1990-02-14
Filing date: 1990-02-14
Publication date: 1991-10-29

Description

[Brief explanation of drawings]

第１図はこの考案の一実施例を示す図、第２図
は従来の実施例を示す図である。１……ＣＰＵ、２……主メモリ、３……リード
信号、４……データバス、５……アドレスバス、
６……不正アドレス検出回路、７……エラー信号
、９……エラー信号保持回路、１０……緊急処理
メモリ、１１……緊急データバス、１３……デー
タセレクタ。なお、図中、同一符号は同一、又は
相当部分を示す。 FIG. 1 is a diagram showing an embodiment of this invention, and FIG. 2 is a diagram showing a conventional embodiment. 1...CPU, 2...Main memory, 3...Read signal, 4...Data bus, 5...Address bus,
6... Invalid address detection circuit, 7... Error signal, 9... Error signal holding circuit, 10... Emergency processing memory, 11... Emergency data bus, 13... Data selector. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims

[Scope of utility model registration request]

A CPU that executes calculations, a main memory that stores programs, an emergency processing memory that is composed of first-in and first-out memory that stores programs for emergency processing, and a read signal from the CPU that uses the main memory address output from the CPU. Illegal address detection circuit that determines whether the address is correct or incorrect based on timing, an error signal holding circuit that holds the error signal output from the incorrect address detection circuit until error processing is completed, and memory switching output from the error signal holding circuit. CP after receiving the signal
Consists of a data selector that switches program transfer to U from main memory to emergency processing memory;
If an error is detected in the main memory address from the PU, the program transfer to the CPU is switched from the main memory to the emergency processing memory using the data selector, and the emergency processing program is transferred to the beginning of the emergency processing memory at the timing of the read signal. CPU sequentially from
An error processing circuit characterized in that the error processing circuit is capable of forwarding the error to the computer and continuing processing.