JPH01144946U - - Google Patents

Description

[Brief explanation of the drawing]

Fig. 1 is a claim correspondence diagram, Fig. 2 is a logic circuit diagram of the multiprocessor system of the present invention, Fig. 3 is a time chart showing the operation of the logic circuit diagram of Fig. 2, and Fig. 4 is a diagram of the present embodiment. 5 is a detailed configuration diagram of the collision detection section in FIG. 4; FIG. 6 is a detailed configuration diagram of the processor monitoring section in FIG. 4; FIGS. 7 and 8
The figures are a time chart showing the memory access operation of the processor in Fig. 4, Fig. 9 is a logic circuit diagram in a conventional multiprocessor system, and Fig. 10 is a time chart showing the operation of the logic circuit in Fig. 9. . 103...first flip-flop circuit, 104
...Second flip-flop circuit, 105...Delay circuit, 110, 111, 112, 113, 116...
Access order/time difference detection circuit, 120, 121
...Access arbitration signal output circuit.

Claims (1)

[Claims for Utility Model Registration] First state detection means for inputting outputs from two processors and detecting the operating state of each processor; and branching and inputting outputs from the two processors; one or two delay means each having a different delay time, and a second state detection means for receiving the output of one of the processors and/or the output from the delay means to detect the operating state of each processor. and order detecting means for detecting the access order of the two processors from the outputs from the first and second state detecting means; and according to the output from the order detecting means, the processor accessed first can be accessed. What is claimed is: 1. A multiprocessor device comprising: arbitration means for controlling a multiprocessor;