JPH0428351U - - Google Patents

Info

Publication number
JPH0428351U
JPH0428351U JP6925190U JP6925190U JPH0428351U JP H0428351 U JPH0428351 U JP H0428351U JP 6925190 U JP6925190 U JP 6925190U JP 6925190 U JP6925190 U JP 6925190U JP H0428351 U JPH0428351 U JP H0428351U
Authority
JP
Japan
Prior art keywords
side circuit
bus
potential
signal
signal line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6925190U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP6925190U priority Critical patent/JPH0428351U/ja
Publication of JPH0428351U publication Critical patent/JPH0428351U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はデータ出力検知装置の回路図、第2図
はデータ出力検知装置をCPUによるメモリアク
セス回路に適用した場合のシステム回路図、第3
図は同システムにおけるCPUに対するレデイ信
号作成動作を示すタイミングチヤート、第4図は
従来のメモリアクセス回路のシステム回路図、第
5図は同回路におけるレデイ信号作成動作を示す
タイミングチヤートである。 1……データバス、2……コンパレータ、3,
4……プルアツプ抵抗、5……データ出力検知装
置。
Fig. 1 is a circuit diagram of a data output detection device, Fig. 2 is a system circuit diagram when the data output detection device is applied to a memory access circuit by a CPU, and Fig. 3 is a system circuit diagram when the data output detection device is applied to a memory access circuit by a CPU.
FIG. 4 is a timing chart showing the ready signal generation operation for the CPU in the same system, FIG. 4 is a system circuit diagram of a conventional memory access circuit, and FIG. 5 is a timing chart showing the ready signal generation operation in the same circuit. 1...Data bus, 2...Comparator, 3,
4...Pull-up resistor, 5...Data output detection device.

Claims (1)

【実用新案登録請求の範囲】 入力されるデータバスの各信号線をプルアツプ
抵抗を介して“H”電位へ接続したバス側回路と
、 前記信号線と同数の信号線をプルアツプ抵抗を
介して“H”電位へ接続した参照側回路と、 バス側回路の各信号線の電位と参照側回路の各
信号線の電位とを比較し、全信号線についての電
位の同一が検出されない場合にデータ検知信号を
出力するコンパレータ とからなるデータバスのデータ出力検知装置。
[Claims for Utility Model Registration] A bus-side circuit in which each signal line of an input data bus is connected to an "H" potential via a pull-up resistor, and a bus-side circuit that connects the same number of signal lines as the signal lines to the "H" potential via a pull-up resistor. Compare the potential of each signal line of the reference side circuit connected to the H” potential, the bus side circuit, and each signal line of the reference side circuit, and if the same potential is not detected for all signal lines, data is detected. A data bus data output detection device consisting of a comparator that outputs a signal.
JP6925190U 1990-06-28 1990-06-28 Pending JPH0428351U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6925190U JPH0428351U (en) 1990-06-28 1990-06-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6925190U JPH0428351U (en) 1990-06-28 1990-06-28

Publications (1)

Publication Number Publication Date
JPH0428351U true JPH0428351U (en) 1992-03-06

Family

ID=31604392

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6925190U Pending JPH0428351U (en) 1990-06-28 1990-06-28

Country Status (1)

Country Link
JP (1) JPH0428351U (en)

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