JPS63114349U - - Google Patents

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Publication number
JPS63114349U
JPS63114349U JP606587U JP606587U JPS63114349U JP S63114349 U JPS63114349 U JP S63114349U JP 606587 U JP606587 U JP 606587U JP 606587 U JP606587 U JP 606587U JP S63114349 U JPS63114349 U JP S63114349U
Authority
JP
Japan
Prior art keywords
master
bus
request signal
bus request
masters
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP606587U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP606587U priority Critical patent/JPS63114349U/ja
Publication of JPS63114349U publication Critical patent/JPS63114349U/ja
Pending legal-status Critical Current

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  • Bus Control (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

図は本考案の一実施例のブロツク図である。 1……ORゲート、21,22,23,24…
…XORゲート、31,32,33,34……ゲ
ート、4……並列固定優先順位決定装置、51,
52,53,54……マスタ、101,102,
103,104……バス要求信号、301,30
2,303,304……強制バス要求信号、50
1,502,503,504……バス使用許可信
号。
The figure is a block diagram of one embodiment of the present invention. 1...OR gate, 21, 22, 23, 24...
...XOR gate, 31, 32, 33, 34... Gate, 4... Parallel fixed priority determination device, 51,
52, 53, 54... Master, 101, 102,
103, 104...Bus request signal, 301, 30
2,303,304...forced bus request signal, 50
1,502,503,504...Bus use permission signal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] マルチマスタシステムバスに接続された複数の
マスタと、該マスタが出力するバス要求信号と該
バス要求信号を並列に入力し、ただ1つのマスタ
に許可信号を出力する並列固定優先順位決定装置
からなるマルチマスタバスシステムにおいて、該
マスタより出力される強制バス要求信号を設け、
該強制バス要求信号が出力されると、該マスタの
バス要求信号を出力し、他マスタのバス要求信号
を禁止する回路を設けたことを特徴とする、マル
チマスタシステムバスの優先順位決定装置。
A multi-master system consisting of multiple masters connected to a system bus, and a parallel fixed priority determination device that inputs the bus request signal outputted by the masters in parallel and outputs a permission signal to only one master. In a multi-master bus system, a forced bus request signal output from the master is provided,
A multi-master system bus priority determination device, comprising a circuit that outputs a bus request signal of the master and inhibits bus request signals of other masters when the forced bus request signal is output.
JP606587U 1987-01-21 1987-01-21 Pending JPS63114349U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP606587U JPS63114349U (en) 1987-01-21 1987-01-21

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP606587U JPS63114349U (en) 1987-01-21 1987-01-21

Publications (1)

Publication Number Publication Date
JPS63114349U true JPS63114349U (en) 1988-07-23

Family

ID=30788228

Family Applications (1)

Application Number Title Priority Date Filing Date
JP606587U Pending JPS63114349U (en) 1987-01-21 1987-01-21

Country Status (1)

Country Link
JP (1) JPS63114349U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02140854A (en) * 1988-11-21 1990-05-30 Nec Corp Bus system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02140854A (en) * 1988-11-21 1990-05-30 Nec Corp Bus system

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