JPH0386458U - - Google Patents
Info
- Publication number
- JPH0386458U JPH0386458U JP14503589U JP14503589U JPH0386458U JP H0386458 U JPH0386458 U JP H0386458U JP 14503589 U JP14503589 U JP 14503589U JP 14503589 U JP14503589 U JP 14503589U JP H0386458 U JPH0386458 U JP H0386458U
- Authority
- JP
- Japan
- Prior art keywords
- bus
- arbitration
- register
- log
- priority numbers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Multi Processors (AREA)
- Bus Control (AREA)
Description
第１図は本考案に従うバス調停回路の一実施例
のブロツク図、第２図は従来のバス調停回路の一
実施例のブロツク図、第３図は比較器６の真理値
を表した図である。図中、１はバスマスタモジユ
ール、２はアービトレーシヨンバスＡＢ０〜ＡＢ
ｎ−１、３はＮＡＮＤゲート素子、４はバス獲得
要求信号ＲＱ、５はモジユールプライオリテイー
信号ＭＮ０〜ＭＮｎ−１、６は比較器、７はバス
獲得受理信号ＡＫ、８はレジスタである。図中、
同一あるいは相当の部分には同一符号を付してあ
る。
FIG. 1 is a block diagram of an embodiment of the bus arbitration circuit according to the present invention, FIG. 2 is a block diagram of an embodiment of the conventional bus arbitration circuit, and FIG. 3 is a diagram showing the truth value of the comparator 6. be. In the figure, 1 is the bus master module, and 2 is the arbitration bus AB 0 to AB.
n-1 , 3 is a NAND gate element, 4 is a bus acquisition request signal RQ, 5 is a module priority signal MN 0 to MN n-1 , 6 is a comparator, 7 is a bus acquisition acceptance signal AK, and 8 is a register. be. In the diagram,
Identical or equivalent parts are given the same reference numerals.
Claims (1)
テイー番号が出力されるｌｏｇ２Ｎ本のアービト
レーシヨンバスを駆動するワイアード接続可能な
ゲート素子と、外部より設定可能なプライオリテ
イー番号を格納するｌｏｇ２Ｎビツトのレジスタ
と、上記レジスタとアービトレーシヨンバス上の
データを入力とする比較器を備えたことを特徴と
するバス調停回路。 A wired connectable gate element that drives log 2 N arbitration buses that outputs priority numbers from a maximum of N bus request modules, and a log 2 N bit that stores externally settable priority numbers. What is claimed is: 1. A bus arbitration circuit comprising: a register; and a comparator whose inputs are the register and data on an arbitration bus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14503589U JPH0386458U (en) | 1989-12-16 | 1989-12-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14503589U JPH0386458U (en) | 1989-12-16 | 1989-12-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0386458U true JPH0386458U (en) | 1991-09-02 |
Family
ID=31691693
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14503589U Pending JPH0386458U (en) | 1989-12-16 | 1989-12-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0386458U (en) |
-
1989
- 1989-12-16 JP JP14503589U patent/JPH0386458U/ja active Pending
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