JPS61185142U - - Google Patents
Info
- Publication number
- JPS61185142U JPS61185142U JP5672986U JP5672986U JPS61185142U JP S61185142 U JPS61185142 U JP S61185142U JP 5672986 U JP5672986 U JP 5672986U JP 5672986 U JP5672986 U JP 5672986U JP S61185142 U JPS61185142 U JP S61185142U
- Authority
- JP
- Japan
- Prior art keywords
- setting
- mode
- information
- mode setting
- bit position
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Bus Control (AREA)
Description
第１図は本考案に係る主要部分を図解的に説明
するために用いる図、第２図は本考案の装置を実
現するための一構成例を示すブロツク図、第３図
は第２図に示した入力パネル２７の具体例を示す
概観正面図である。
図において１１はモード設定レジスタ、２２は
共通バス、２４はＤＭＡ制御回路、２５はインタ
フエース回路、２７は入力パネルである。
Figure 1 is a diagram used to schematically explain the main parts of the present invention, Figure 2 is a block diagram showing one configuration example for realizing the device of the present invention, and Figure 3 is similar to Figure 2. FIG. 3 is a schematic front view showing a specific example of the input panel 27 shown in FIG. In the figure, 11 is a mode setting register, 22 is a common bus, 24 is a DMA control circuit, 25 is an interface circuit, and 27 is an input panel.
Claims (1)
置対応で設定するモード設定レジスタと、該共通
バスに接続され該モード設定レジスタに設定され
たデータに従つたモードで動作する中央処理装置
と、該モード設定レジスタに対し前記データを設
定するために設けられた複数の設定キーを具備す
る入力パネルとを含んでなるコンピユータシステ
ムにおける情報のセツト装置において、 前記入力パネル内の１つの前記設定キーを操作
したとき、これに対応するモード設定情報および
前記モード設定レジスタのビツト位置情報を作成
するインタフエース回路と、該インタフエース回
路に接続するＤＭＡ（Ｄｉｒｅｃｔ Ｍｅｍｏｒ
ｙ Ａｃｃｅｓｓ）制御回路とを設け、前記入力
パネル内で前記設定キーが操作されたときに、前
記インタフエース回路にて当該操作された設定キ
ーに対応した前記のモード設定情報ならびにビツ
ト位置情報を作成し、当該ビツト位置情報に従い
前記モード設定情報を、前記ＤＭＡ制御回路によ
るＤＭＡ制御のもとに、前記共通バスを経由して
前記モード設定レジスタ内の所定のビツト位置に
セツトすることを特徴とする情報のセツト装置。[Claims for Utility Model Registration] A mode setting register that is connected to a common bus and sets a predetermined mode corresponding to each bit position, and a mode that is connected to the common bus and operates in a mode according to the data set in the mode setting register. An information setting device for a computer system comprising: a central processing unit for setting the data to the mode setting register; and an input panel having a plurality of setting keys provided for setting the data to the mode setting register; an interface circuit that creates mode setting information and bit position information of the mode setting register when one of the setting keys is operated; and a DMA (Direct Memory) connected to the interface circuit.
y Access) control circuit, and when the setting key is operated in the input panel, the mode setting information and bit position information corresponding to the operated setting key are created in the interface circuit. The mode setting information is set to a predetermined bit position in the mode setting register via the common bus under DMA control by the DMA control circuit in accordance with the bit position information. Information setting device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5672986U JPS61185142U (en) | 1986-04-17 | 1986-04-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5672986U JPS61185142U (en) | 1986-04-17 | 1986-04-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61185142U true JPS61185142U (en) | 1986-11-18 |
Family
ID=30580604
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5672986U Pending JPS61185142U (en) | 1986-04-17 | 1986-04-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61185142U (en) |
-
1986
- 1986-04-17 JP JP5672986U patent/JPS61185142U/ja active Pending
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