JPH0242138U

JPH0242138U -

Info

Publication number: JPH0242138U
Application number: JP12194888U
Authority: JP
Priority date: 1988-09-16
Filing date: 1988-09-16
Publication date: 1990-03-23

Description

[Brief explanation of drawings]

第１図は、本考案の実施例を示すブロツク図、
第２図は、第１図に示された実施例の動作を示す
タイミング図、第３図は、本考案の他の実施例を
示すブロツク図、第４図は、第３図に示された実
施例の動作を示すタイミング図である。１……シフトレジスタ、２……データレジスタ
、３……データバス、４……転送回路、５……ク
ロツク発生回路、８……計数回路、９……制御回
路、１０……割込み要求フラグ、１１……比較回
路、１２……フラグ、１３……反転回路。 FIG. 1 is a block diagram showing an embodiment of the present invention;
2 is a timing diagram showing the operation of the embodiment shown in FIG. 1, FIG. 3 is a block diagram showing another embodiment of the present invention, and FIG. 4 is a timing diagram showing the operation of the embodiment shown in FIG. 3. FIG. 3 is a timing diagram showing the operation of the embodiment. 1... Shift register, 2... Data register, 3... Data bus, 4... Transfer circuit, 5... Clock generation circuit, 8... Counting circuit, 9... Control circuit, 10... Interrupt request flag, 11... Comparison circuit, 12... Flag, 13... Inverting circuit.

Claims

[Claims for Utility Model Registration] (1) A shift register that serially inputs or outputs data consisting of predetermined bits based on a synchronous clock, a counting circuit that counts the synchronous clock for 2 data, and the counting circuit is synchronous. A control circuit that generates a first control signal and a second control signal when the clock is counted for one data and when it is counted for two data, respectively, and the data input to the shift register or the data to be transferred. a data register that holds a data register; a data transfer circuit that transfers data from the shift register to the data register and from the data register to the shift register based on the first control signal; A data input/output device comprising: a comparison circuit that compares data in the data register and the shift register based on the second control signal. (2) In a single-chip microcomputer equipped with an internal interrupt function, there is a shift register that serially inputs or outputs data consisting of predetermined bits based on a synchronous clock, and a counting circuit that counts the synchronous clock for two pieces of data. and a control circuit that generates a first control signal and a second control signal when the counting circuit counts the synchronous clock for one data and when it counts for two data, respectively, and is connected to the internal data bus. , a data register that holds data input to the shift register or data to be transferred; and a first control signal that controls data transfer from the shift register to the data register and from the data register to the shift register. a data transfer circuit based on the data transfer circuit; a comparison circuit that compares data in the data register and the shift register based on the second control signal when data is input; a match flag, and an interrupt request is generated by the second control signal. (3) In claim 1 or 2, an inversion circuit that selectively inverts and non-inverts data is provided between the shift register and the data transfer circuit, and the comparison circuit A data input/output device and a microcomputer equipped with the same, characterized by comparing non-inverted data and inverted data of data input to the device.