JPH03113443U - - Google Patents

Description

[Brief explanation of drawings]

Figure 1 is a diagram showing one embodiment of this invention, Figure 2
The figure shows the timing chart, and FIG. 3 is a diagram used to show an example of the conventional device.
FIG. 4 is a diagram showing the timing chart. In the figure, 1 is an input register, 2 is a data selector, 3 is an interrupt register, 4 is a data interrupt device (data highway bit), 5 is an interrupt input, 6 is input data, 7 is a transfer clock output, 8 is interrupt data, 9 is the interrupt clock, 10 is the data sent from the input register, 1
1 is output data, 12 is a gate, 13 is a transfer clock input, 14 is an interrupt request, 15 is an interrupt control circuit, 16 is a transfer stop output, and 17 is a selector signal. It should be noted that the same or corresponding parts in the drawings are designated by the same reference numerals.

Claims (1)

[Scope of utility model registration request] In a data interrupt device that interrupts data that is being transported, in order to interrupt data, control the data selector and interrupt register using the interrupt input, and at the same time output the transport clock input as the transport clock output. an input register that takes in input data using the transport clock output and sends out the original data at the same time; an interrupt register that takes in interrupt data using the interrupt clock and sends out the interrupt data under the control of the gate; Equipped with a data selector that switches between sending data controlled by a gate and sent from an input register as output data, or sending data sent from an input register to an interrupt register and sending the original data of the interrupt register as output data. A data interrupt device featuring: