JPH0314827U - - Google Patents
Info
- Publication number
- JPH0314827U JPH0314827U JP7491589U JP7491589U JPH0314827U JP H0314827 U JPH0314827 U JP H0314827U JP 7491589 U JP7491589 U JP 7491589U JP 7491589 U JP7491589 U JP 7491589U JP H0314827 U JPH0314827 U JP H0314827U
- Authority
- JP
- Japan
- Prior art keywords
- controlling
- circuit
- positive feedback
- feedback circuit
- delay time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 1
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
- Information Transfer Systems (AREA)
- Pulse Circuits (AREA)
Description
第１図は本案の回路構成を示すブロツク図、第
２図は本案の一実施例を示すシリアルインタフエ
ースのシステム構成を示すブロツク図、第３図は
第２図で示した一実施例におけるタイミング・チ
ヤートである。
第１図：１……正帰還回路、２，３……制御信
号、４……入力バス、５……出力バス、６……ゲ
ート回路。第２図：１……データレジスタ、２…
…転送クロツク信号、３……遅延時間制御回路、
４……制御信号、５……受信データ信号、６……
送信データ信号、７……制御回路３より出力され
た信号。
Fig. 1 is a block diagram showing the circuit configuration of the present invention, Fig. 2 is a block diagram showing the system configuration of a serial interface showing an embodiment of the present invention, and Fig. 3 is a timing diagram of the embodiment shown in Fig. 2.・It is a chat. Figure 1: 1... Positive feedback circuit, 2, 3... Control signal, 4... Input bus, 5... Output bus, 6... Gate circuit. Figure 2: 1...data register, 2...
...Transfer clock signal, 3...Delay time control circuit,
4... Control signal, 5... Received data signal, 6...
Transmission data signal, 7... Signal output from control circuit 3.
Claims (1)
バスと正帰還回路の接続点の制御手段を備えてい
るか、もしくは正帰還回路に制御手段を備えた、
データ入出力の遅延時間の有無を制御することを
特徴とするシユミツト回路。 ２ 請求の範囲第１項記載のシユミツト回路を有
し、データ入出力の遅延時間の有無を制御するこ
とを特徴とするデジタルシステム。[Claims for Utility Model Registration] 1. Consisting of a gate circuit having a positive feedback circuit,
comprising means for controlling the connection point between the bus and the positive feedback circuit, or comprising means for controlling the positive feedback circuit;
A Schmitt circuit characterized by controlling the presence or absence of a data input/output delay time. 2. A digital system comprising the Schmitt circuit according to claim 1 and controlling the presence or absence of a data input/output delay time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7491589U JPH0314827U (en) | 1989-06-28 | 1989-06-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7491589U JPH0314827U (en) | 1989-06-28 | 1989-06-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0314827U true JPH0314827U (en) | 1991-02-14 |
Family
ID=31615032
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7491589U Pending JPH0314827U (en) | 1989-06-28 | 1989-06-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0314827U (en) |
-
1989
- 1989-06-28 JP JP7491589U patent/JPH0314827U/ja active Pending
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