JPS6286749U - - Google Patents

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Publication number
JPS6286749U
JPS6286749U JP17742285U JP17742285U JPS6286749U JP S6286749 U JPS6286749 U JP S6286749U JP 17742285 U JP17742285 U JP 17742285U JP 17742285 U JP17742285 U JP 17742285U JP S6286749 U JPS6286749 U JP S6286749U
Authority
JP
Japan
Prior art keywords
communication path
communication
switching control
control device
output device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17742285U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP17742285U priority Critical patent/JPS6286749U/ja
Publication of JPS6286749U publication Critical patent/JPS6286749U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本考案の一実施例の機能ブロツク図
、第2図は、本考案の伝送のタイムチヤート及び
、通信路バイパス回路の設定タイミング図、第3
図は、伝送信号を中継する場合に受信を完了し、
送出する場合と本バイパス回路を使用した場合の
遅れ時間とキヤラクタ数の関係図、第4図はソフ
トウエア処理方法と伝送遅延時間の関係線図であ
る。 1……マスター入出力装置、2……回線切替制
御装置、8……マイクロプロセツサー、9……伝
送制御LSI、10……回線切換回路、11……
通信路バイパス回路、12……切替制御接点回路
、13……システムバス、14……発振回路。
FIG. 1 is a functional block diagram of an embodiment of the present invention, FIG. 2 is a transmission time chart of the present invention and a setting timing diagram of a communication path bypass circuit, and FIG.
The figure shows when the transmission signal is relayed, the reception is completed,
FIG. 4 is a diagram showing the relationship between the delay time and the number of characters when transmitting data and when using this bypass circuit, and FIG. 4 is a diagram showing the relationship between the software processing method and the transmission delay time. 1... Master input/output device, 2... Line switching control device, 8... Microprocessor, 9... Transmission control LSI, 10... Line switching circuit, 11...
Communication path bypass circuit, 12... switching control contact circuit, 13... system bus, 14... oscillation circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数台の中央処理装置と、1台の入出力装置と
よりなる非同期通信網に於いて、通信を中断する
ことなく、1回の特定コマンドにより通信路を切
替、その後に送出される通信データを、遅延させ
ることを防ぐバイパス通信路を設けたことを特徴
とするデジタル通信路切替制御装置。
In an asynchronous communication network consisting of multiple central processing units and one input/output device, the communication path can be switched with one specific command without interrupting communication, and the communication data sent after that can be changed. , a digital communication path switching control device characterized in that a bypass communication path is provided to prevent delays.
JP17742285U 1985-11-20 1985-11-20 Pending JPS6286749U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17742285U JPS6286749U (en) 1985-11-20 1985-11-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17742285U JPS6286749U (en) 1985-11-20 1985-11-20

Publications (1)

Publication Number Publication Date
JPS6286749U true JPS6286749U (en) 1987-06-03

Family

ID=31118607

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17742285U Pending JPS6286749U (en) 1985-11-20 1985-11-20

Country Status (1)

Country Link
JP (1) JPS6286749U (en)

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