JPH0279643U - - Google Patents
Info
- Publication number
- JPH0279643U JPH0279643U JP15985488U JP15985488U JPH0279643U JP H0279643 U JPH0279643 U JP H0279643U JP 15985488 U JP15985488 U JP 15985488U JP 15985488 U JP15985488 U JP 15985488U JP H0279643 U JPH0279643 U JP H0279643U
- Authority
- JP
- Japan
- Prior art keywords
- data
- synchronization pattern
- circuit
- invert
- transmission system
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 6
- 238000001514 detection method Methods 0.000 description 3
- 230000001360 synchronised effect Effects 0.000 description 3
Description
第１図はこの考案の一実施例による同期回路の
ブロツク図、第２図は第１図におけるデータのシ
ーケンス図、第３図はこの考案の他の実施例を示
す同期回路のブロツク図、第４図は第３図におけ
るデータのシーケンス図、第５図は従来の同期回
路のブロツク図、第６図は第５図のデータのシー
ケンス図である。
図において、１はデータ受信回路、２は同期パ
ターン検出回路、３はデータ反転回路、４はデー
タ選択回路、５はデータ入力端子、６は同期パタ
ーン検出出力端子、７は受信データ出力端子、８
はデータ選択入力端子、９は同期パターン付加回
路、１０は同期パターン発生回路、１１は同期パ
ターン反転回路、１２は同期パターン選択回路、
１３はデータ（送信）入力端子、１４は送信デー
タ出力端子、１５は同期パターン選択入力端子、
１６はパターン検出回路を示す。なお、図中、同
一符号は同一、又は相当部分を示す。
Fig. 1 is a block diagram of a synchronous circuit according to an embodiment of this invention, Fig. 2 is a sequence diagram of data in Fig. 1, and Fig. 3 is a block diagram of a synchronous circuit showing another embodiment of this invention. 4 is a data sequence diagram in FIG. 3, FIG. 5 is a block diagram of a conventional synchronous circuit, and FIG. 6 is a data sequence diagram in FIG. In the figure, 1 is a data reception circuit, 2 is a synchronization pattern detection circuit, 3 is a data inversion circuit, 4 is a data selection circuit, 5 is a data input terminal, 6 is a synchronization pattern detection output terminal, 7 is a received data output terminal, 8
is a data selection input terminal, 9 is a synchronization pattern addition circuit, 10 is a synchronization pattern generation circuit, 11 is a synchronization pattern inversion circuit, 12 is a synchronization pattern selection circuit,
13 is a data (transmission) input terminal, 14 is a transmission data output terminal, 15 is a synchronization pattern selection input terminal,
16 indicates a pattern detection circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
ブシステムで構成されているシステムにおいて、
前記サブシステムにおける伝送系の同期パターン
を容易に切換えられる様に送信側は同期パターン
の反転、受信側は受信データの反転を可能とした
ことを特徴とする同期回路。 In a system where the data transmission system itself is composed of several subsystems,
A synchronization circuit characterized in that the transmission side can invert the synchronization pattern and the reception side can invert the received data so that the synchronization pattern of the transmission system in the subsystem can be easily switched.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15985488U JPH0279643U (en) | 1988-12-07 | 1988-12-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15985488U JPH0279643U (en) | 1988-12-07 | 1988-12-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0279643U true JPH0279643U (en) | 1990-06-19 |
Family
ID=31441423
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15985488U Pending JPH0279643U (en) | 1988-12-07 | 1988-12-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0279643U (en) |
-
1988
- 1988-12-07 JP JP15985488U patent/JPH0279643U/ja active Pending
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