JPS6157751U - - Google Patents

Info

Publication number
JPS6157751U
JPS6157751U JP1984142633U JP14263384U JPS6157751U JP S6157751 U JPS6157751 U JP S6157751U JP 1984142633 U JP1984142633 U JP 1984142633U JP 14263384 U JP14263384 U JP 14263384U JP S6157751 U JPS6157751 U JP S6157751U
Authority
JP
Japan
Prior art keywords
signal
circuit
outputs
period
detection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1984142633U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1984142633U priority Critical patent/JPS6157751U/ja
Priority to KR2019850009989U priority patent/KR890007495Y1/en
Publication of JPS6157751U publication Critical patent/JPS6157751U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H04N5/06—Generation of synchronising signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/64—Generators producing trains of pulses, i.e. finite sequences of pulses
    • H03K3/66—Generators producing trains of pulses, i.e. finite sequences of pulses by interrupting the output of a generator
    • H03K3/70—Generators producing trains of pulses, i.e. finite sequences of pulses by interrupting the output of a generator time intervals between all adjacent pulses of one train being equal

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Synchronizing For Television (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案になる等価パルス検出回路の基
本的構成を示す図、第２図は本考案になる等価パ
ルス検出回路の第１実施例のブロツク系統図、第
３図はハーフＨキラー回路の一例を示す回路図、
第４図は第２図に示す本考案になる等価パルス検
出回路の第１実施例の動作を説明するための図、
第５図は本考案になる等価パルス検出回路の第２
実施例のブロツク系統図、第６図は第５図に示す
本考案になる等価パルス検出回路の第２実施例の
動作を説明するための図である。 ａ，２…ハーフＨキラー回路、ｂ…等価パルス
除去回路、１…入力端子、３，４…モノマルチ回
路、５，９…アンド（ＡＮＤ）回路、６…エクス
クルーシブオア（ＥＸＯＲ）回路、７…出力端子
、８…ナンド（ＮＡＮＤ）回路、ＦＦ１，ＦＦ２
…フリツプフロツプ回路、Ｎ１，Ｎ２…反転回路
、Ｄ１，Ｄ２…ダイオード、Ｒ１，Ｒ２…抵抗器
、Ｃ１，Ｃ２…コンデンサ。 Fig. 1 is a diagram showing the basic configuration of the equivalent pulse detection circuit according to the present invention, Fig. 2 is a block system diagram of the first embodiment of the equivalent pulse detection circuit according to the present invention, and Fig. 3 is a half H killer circuit. A circuit diagram showing an example of
FIG. 4 is a diagram for explaining the operation of the first embodiment of the equivalent pulse detection circuit according to the present invention shown in FIG.
Figure 5 shows the second equivalent pulse detection circuit according to the present invention.
FIG. 6, a block system diagram of the embodiment, is a diagram for explaining the operation of the second embodiment of the equivalent pulse detection circuit according to the present invention shown in FIG. a, 2... Half H killer circuit, b... Equivalent pulse removal circuit, 1... Input terminal, 3, 4... Mono multi circuit, 5, 9... AND (AND) circuit, 6... Exclusive OR (EXOR) circuit, 7... Output terminal, 8...NAND circuit, FF 1 , FF 2
 ...Flip-flop circuit, N1 , N2 ...Inverting circuit, D1 , D2 ...Diode, R1 , R2 ...Resistor, C1 , C2 ...Capacitor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 映像信号の複合同期信号が供給され水平同期信
号の周期のパルス信号を出力するハーフＨキラー
回路と、前記複合同期信号及び前記ハーフＨキラ
ー回路の出力信号が供給され前記水平同期信号と
前記水平同期信号の周期の1/2の期間だけ位相が
異なる等価パルスの伝送位置に対応する検出信号
を出力する検出信号発生回路とを備えた等価パル
ス検出回路。 A half-H killer circuit is supplied with a composite synchronization signal of a video signal and outputs a pulse signal having the period of the horizontal synchronization signal; An equivalent pulse detection circuit comprising a detection signal generation circuit that outputs a detection signal corresponding to a transmission position of an equivalent pulse whose phase differs by 1/2 of the signal period.
JP1984142633U 1984-09-20 1984-09-20 Pending JPS6157751U (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP1984142633U JPS6157751U (en) 1984-09-20 1984-09-20
KR2019850009989U KR890007495Y1 (en) 1984-09-20 1985-08-02 Equalizing pulse detecting circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984142633U JPS6157751U (en) 1984-09-20 1984-09-20

Publications (1)

Publication Number Publication Date
JPS6157751U true JPS6157751U (en) 1986-04-18

Family

ID=15319883

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984142633U Pending JPS6157751U (en) 1984-09-20 1984-09-20

Country Status (2)

Country Link
JP (1) JPS6157751U (en)
KR (1) KR890007495Y1 (en)

Also Published As

Publication number Publication date
KR860004415U (en) 1986-05-01
KR890007495Y1 (en) 1989-10-26

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