JPS6355628U - - Google Patents
Info
- Publication number
- JPS6355628U JPS6355628U JP14716186U JP14716186U JPS6355628U JP S6355628 U JPS6355628 U JP S6355628U JP 14716186 U JP14716186 U JP 14716186U JP 14716186 U JP14716186 U JP 14716186U JP S6355628 U JPS6355628 U JP S6355628U
- Authority
- JP
- Japan
- Prior art keywords
- flip
- input signal
- flop
- noise removal
- clocks
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Manipulation Of Pulses (AREA)
Description
第１図はこの考案の実施例であるノイズ除去回
路の回路図を示す。第２図、第３図は入力信号が
正論理の場合のタイミングチヤート、負論理の場
合のタイミングチヤートをそれぞれ示す。また第
４図は、従来のノイズ除去回路の回路図である。
１，２…Ｄ―フリツプフロツプ、４…（論理ゲ
ートを構成する）ＥＸ―ＮＯＲゲート。
FIG. 1 shows a circuit diagram of a noise removal circuit which is an embodiment of this invention. FIGS. 2 and 3 show a timing chart when the input signal is positive logic and a timing chart when the input signal is negative logic, respectively. Further, FIG. 4 is a circuit diagram of a conventional noise removal circuit. 1, 2...D-flip-flop, 4...EX-NOR gate (constituting a logic gate).
Claims (1)
ツク信号によりタイミング制御される２つのＤ―
フリツプフロツプと、両Ｄ―フリツプフロツプの
出力の一致を判別する論理ゲートで構成されたノ
イズ除去回路。 Two D-clocks are supplied with a common input signal and whose timing is controlled by mutually opposite clock signals.
A noise removal circuit consisting of a flip-flop and a logic gate that determines whether the outputs of both D-flip-flops match.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14716186U JPS6355628U (en) | 1986-09-25 | 1986-09-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14716186U JPS6355628U (en) | 1986-09-25 | 1986-09-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6355628U true JPS6355628U (en) | 1988-04-14 |
Family
ID=31060273
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14716186U Pending JPS6355628U (en) | 1986-09-25 | 1986-09-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6355628U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012008164A1 (en) * | 2010-07-16 | 2012-01-19 | パナソニック株式会社 | Noise elimination device, noise elimination method and vehicle in-built display device using same noise elimination device |
-
1986
- 1986-09-25 JP JP14716186U patent/JPS6355628U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012008164A1 (en) * | 2010-07-16 | 2012-01-19 | パナソニック株式会社 | Noise elimination device, noise elimination method and vehicle in-built display device using same noise elimination device |