JPS63169713U

JPS63169713U -

Info

Publication number: JPS63169713U
Application number: JP6026687U
Authority: JP
Priority date: 1987-04-21
Filing date: 1987-04-21
Publication date: 1988-11-04

Description

[Brief explanation of drawings]

第１図は本考案の一実施例を示す回路構成図、
第２図は第１図の動作を説明するタイムチヤート
、第３図は第１図の一部を構成する第１、第２の
フリツプフロツプ回路の機能を説明する真理値表
、第４図は従来例を示す回路構成図、第５図は第
４図の動作を説明するタイムチヤートである。３……第１のフリツプフロツプ回路、４……第
２のフリツプフロツプ回路、２０……パルス信号
形成装置、ＭＣＰ……マスタクロツク信号、ＯＵ
Ｔ１（ＣＬＯＣＫ）……第１のパルス信号、ＲＥ
ＳＴ１……第１のリセツト信号、ＲＥＳＴ２……
第２のリセツト信号、ＯＵＴ２……第２のパルス
信号。 FIG. 1 is a circuit diagram showing an embodiment of the present invention;
Fig. 2 is a time chart explaining the operation of Fig. 1, Fig. 3 is a truth table explaining the functions of the first and second flip-flop circuits forming a part of Fig. 1, and Fig. 4 is a conventional flip-flop circuit. A circuit configuration diagram showing an example, and FIG. 5 is a time chart explaining the operation of FIG. 4. 3...First flip-flop circuit, 4...Second flip-flop circuit, 20...Pulse signal forming device, MCP...Master clock signal, OU
T1 (CLOCK)...first pulse signal, RE
ST1...first reset signal, REST2...
Second reset signal, OUT2... second pulse signal.

Claims

[Scope of utility model registration request]

A first flip-flop circuit that forms and outputs a pulse signal having the same frequency as the clock signal based on an input clock signal of a constant frequency; and a first flip-flop circuit that latches and outputs input data based on the output of the first flip-flop circuit. and a second flip-flop circuit, the pulse signal forming circuit is provided with a first reset signal for the first flip-flop having different output timings based on the output of the first flip-flop circuit. A pulse signal forming device characterized in that it is additionally equipped with a reset signal forming means having a function of forming and outputting a second reset signal for the second flip-flop circuit.