JPH01135844U - - Google Patents
Info
- Publication number
- JPH01135844U JPH01135844U JP3285988U JP3285988U JPH01135844U JP H01135844 U JPH01135844 U JP H01135844U JP 3285988 U JP3285988 U JP 3285988U JP 3285988 U JP3285988 U JP 3285988U JP H01135844 U JPH01135844 U JP H01135844U
- Authority
- JP
- Japan
- Prior art keywords
- data
- output circuit
- clock
- circuit
- clock signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 claims description 7
- 230000000630 rising effect Effects 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Dc Digital Transmission (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Description
第１図は本考案実施例の回路構成を示す図、第
２図と第３図は本考案実施例のタイミングチヤー
トを示す図、第４図は従来例のタイミングチヤー
トを示す図である。
１……送信側、２……受信側、３……伝送路、
４……出力データラツチ、５……クロツク２分周
器、６……データ伝送路、７……クロツク伝送路
、９……入力データラツチ、１０……クロツクエ
ツジ統一回路、１１……遅延回路、１２……反一
致回路。
FIG. 1 is a diagram showing the circuit configuration of an embodiment of the present invention, FIGS. 2 and 3 are diagrams showing a timing chart of the embodiment of the present invention, and FIG. 4 is a diagram showing a timing chart of a conventional example. 1... Sending side, 2... Receiving side, 3... Transmission path,
4... Output data latch, 5... Clock 2 frequency divider, 6... Data transmission line, 7... Clock transmission line, 9... Input data latch, 10... Clock unified circuit, 11... Delay circuit, 12... ...Anti-coincidence circuit.
Claims (1)
びにデータ入力回路を有し、クロツク出力回路か
らのクロツク信号に同期してデータ出力回路から
データを出力すると共に伝送路を通過したデータ
をデータ入力回路にて入力するデータ伝送装置に
おいて、クロツク出力回路からのクロツク信号の
立ち上がりエツジと立ち下がりエツジにおいてと
もに立ち上がりエツジあるいは立ち下がりエツジ
をもつクロツク信号を生成するクロツク生成回路
と、このクロツク生成回路からのクロツク信号の
立ち上がりエツジまたは立ち下がりエツジに応じ
てデータを入力するデータ入力回路とを備えたこ
とを特徴とするデータ伝送装置。 It has a clock output circuit, a data output circuit, a transmission path, and a data input circuit, and outputs data from the data output circuit in synchronization with the clock signal from the clock output circuit, and also outputs data that has passed through the transmission path to the data input circuit. The input data transmission device includes a clock generation circuit that generates a clock signal that has a rising edge or a falling edge on both the rising edge and the falling edge of the clock signal from the clock output circuit, and A data transmission device comprising: a data input circuit that inputs data in response to a rising edge or a falling edge.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3285988U JPH01135844U (en) | 1988-03-11 | 1988-03-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3285988U JPH01135844U (en) | 1988-03-11 | 1988-03-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01135844U true JPH01135844U (en) | 1989-09-18 |
Family
ID=31259456
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3285988U Pending JPH01135844U (en) | 1988-03-11 | 1988-03-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01135844U (en) |
-
1988
- 1988-03-11 JP JP3285988U patent/JPH01135844U/ja active Pending
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