JPS5850755U - Signal disconnection detection circuit - Google Patents

Signal disconnection detection circuit

Info

Publication number
JPS5850755U
JPS5850755U JP1981140345U JP14034581U JPS5850755U JP S5850755 U JPS5850755 U JP S5850755U JP 1981140345 U JP1981140345 U JP 1981140345U JP 14034581 U JP14034581 U JP 14034581U JP S5850755 U JPS5850755 U JP S5850755U
Authority
JP
Japan
Prior art keywords
circuit
pulse
detection circuit
disconnection detection
pulses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1981140345U
Other languages
Japanese (ja)
Inventor
隆志 木原
康弘 田中
Original Assignee
富士通株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通株式会社 filed Critical 富士通株式会社
Priority to JP1981140345U priority Critical patent/JPS5850755U/en
Publication of JPS5850755U publication Critical patent/JPS5850755U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は光受信部の概略ブロック図、第2図は本考案の
一実施例を示す回路図、第3図および第4図は各部信号
波形図である。 図中、10は立下り微分回路、11は立下り微分回路、
DLl〜DL3は遅延回路、A1はアンドゲートである
FIG. 1 is a schematic block diagram of an optical receiver, FIG. 2 is a circuit diagram showing an embodiment of the present invention, and FIGS. 3 and 4 are signal waveform diagrams of each part. In the figure, 10 is a falling differential circuit, 11 is a falling differential circuit,
DLl to DL3 are delay circuits, and A1 is an AND gate.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力信号の前縁および後縁に対応してそれぞれ第1およ
び第2のパルスを発生する回路と、該第1のパルスを正
規のデータ信号の1タイムスロツトの1,2・・・・・
・0倍遅延させ、それらn個の遅延パルスを合成する回
路と、該合成回路が出力する遅延パルス群と前記第2の
パルスとを入力され、該第2のパルスが時間軸上で該遅
延パルスのいずれとも一致しないとき出力を生じるゲー
ト回路とを備えることを特徴とする信号断検出回路。
a circuit for generating first and second pulses corresponding to leading and trailing edges of an input signal, respectively;
- A circuit that delays the n delayed pulses by 0 times and synthesizes the n delayed pulses, and the delayed pulse group output from the synthesis circuit and the second pulse are input, and the second pulse is input with the delay on the time axis. A signal disconnection detection circuit comprising: a gate circuit that produces an output when the pulse does not match any of the pulses.
JP1981140345U 1981-09-21 1981-09-21 Signal disconnection detection circuit Pending JPS5850755U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1981140345U JPS5850755U (en) 1981-09-21 1981-09-21 Signal disconnection detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1981140345U JPS5850755U (en) 1981-09-21 1981-09-21 Signal disconnection detection circuit

Publications (1)

Publication Number Publication Date
JPS5850755U true JPS5850755U (en) 1983-04-06

Family

ID=29933509

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1981140345U Pending JPS5850755U (en) 1981-09-21 1981-09-21 Signal disconnection detection circuit

Country Status (1)

Country Link
JP (1) JPS5850755U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05236521A (en) * 1992-02-19 1993-09-10 Nec Corp Tone detecting circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05236521A (en) * 1992-02-19 1993-09-10 Nec Corp Tone detecting circuit

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