JPS5834451U - Signal sending circuit - Google Patents
Signal sending circuitInfo
- Publication number
- JPS5834451U JPS5834451U JP1981126457U JP12645781U JPS5834451U JP S5834451 U JPS5834451 U JP S5834451U JP 1981126457 U JP1981126457 U JP 1981126457U JP 12645781 U JP12645781 U JP 12645781U JP S5834451 U JPS5834451 U JP S5834451U
- Authority
- JP
- Japan
- Prior art keywords
- signal sending
- buffer
- sending circuit
- signal
- inputted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Mobile Radio Communication Systems (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来−のブロック図、第２図は第１図の従来例
を説明するためのタイミングチャート、第３図は第１図
の欠点を補正した回路の要部の回路図、第４図は本考案
の実施例のブロック図、第５図は第４図を説明するため
のタイミングチャート。Fig. 1 is a conventional block diagram, Fig. 2 is a timing chart for explaining the conventional example of Fig. 1, Fig. 3 is a circuit diagram of the main part of the circuit that corrects the drawbacks of Fig. 1, and Fig. 4 is a timing chart for explaining the conventional example of Fig. 1. The figure is a block diagram of an embodiment of the present invention, and FIG. 5 is a timing chart for explaining FIG. 4.
Claims (1)
を各々バッファを介して入力し、各々低域通過フィルタ
を通過させて波形整形した後、両者を加算回路によって
合成し、２波並列トーン信号とする信号送出回路であっ
て、前記２つの信号中の一方が入力するバッファをノン
インバーテイングバッファとし他方が入力するバッファ
をインバーテイングバッファで構成したことを特徴とす
る信号送出回路。Input signals at the logic circuit level with two different frequencies are input through buffers, each passes through a low-pass filter to shape the waveform, and then they are combined by an adder circuit to form a two-wave parallel tone signal. 1. A signal sending circuit, characterized in that a buffer into which one of the two signals is inputted is a non-inverting buffer, and a buffer into which the other signal is inputted is an inverting buffer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1981126457U JPS5834451U (en) | 1981-08-28 | 1981-08-28 | Signal sending circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1981126457U JPS5834451U (en) | 1981-08-28 | 1981-08-28 | Signal sending circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5834451U true JPS5834451U (en) | 1983-03-05 |
Family
ID=29920243
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1981126457U Pending JPS5834451U (en) | 1981-08-28 | 1981-08-28 | Signal sending circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5834451U (en) |
-
1981
- 1981-08-28 JP JP1981126457U patent/JPS5834451U/en active Pending
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