JPS581987U - border circuit - Google Patents

border circuit

Info

Publication number
JPS581987U
JPS581987U JP9362181U JP9362181U JPS581987U JP S581987 U JPS581987 U JP S581987U JP 9362181 U JP9362181 U JP 9362181U JP 9362181 U JP9362181 U JP 9362181U JP S581987 U JPS581987 U JP S581987U
Authority
JP
Japan
Prior art keywords
circuit
text
border
border circuit
fidori
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9362181U
Other languages
Japanese (ja)
Inventor
淳也 門間
Original Assignee
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to JP9362181U priority Critical patent/JPS581987U/en
Publication of JPS581987U publication Critical patent/JPS581987U/en
Pending legal-status Critical Current

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  • Digital Computer Display Output (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のふちどり処理装置の一具体例を示すブロ
ック図、第2図は第1図の装置各部の波形図、第3図は
本考案によるふちどり処理回路の一実施例を示すブロッ
ク図、第4図は第3図のブロック図各部の信号波形図で
ある。 20・・・入力端子、21・・・遅延回路、22・・・
遅延回路、23・・・合成回路、24・・・合成回路、
25・・・合成回路、26・・・出力端子。
FIG. 1 is a block diagram showing a specific example of a conventional border processing device, FIG. 2 is a waveform diagram of each part of the device shown in FIG. 1, and FIG. 3 is a block diagram showing an embodiment of a border processing circuit according to the present invention. , FIG. 4 is a signal waveform diagram of each part of the block diagram of FIG. 3. 20...Input terminal, 21...Delay circuit, 22...
delay circuit, 23... synthesis circuit, 24... synthesis circuit,
25...Synthesizing circuit, 26...Output terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 文字図形情報端末の表示回路において、低域フ−イルタ
、それぞれ異なった振幅制限レベルを持った2つのリミ
ッタ回路、波形整形回路およびアナログ加算回路で構成
され、”文字と背景の境界にふちどりを付加することが
できる構成を備えている“ふぢどり回路。
The display circuit of a text/graphic information terminal consists of a low-pass filter, two limiter circuits each with different amplitude limiting levels, a waveform shaping circuit, and an analog addition circuit, and is used to add borders to the border between text and background. A “fidori circuit” that has a configuration that can be used.
JP9362181U 1981-06-26 1981-06-26 border circuit Pending JPS581987U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9362181U JPS581987U (en) 1981-06-26 1981-06-26 border circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9362181U JPS581987U (en) 1981-06-26 1981-06-26 border circuit

Publications (1)

Publication Number Publication Date
JPS581987U true JPS581987U (en) 1983-01-07

Family

ID=29888581

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9362181U Pending JPS581987U (en) 1981-06-26 1981-06-26 border circuit

Country Status (1)

Country Link
JP (1) JPS581987U (en)

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