JPS59187271U - Synchronous separation circuit - Google Patents
Synchronous separation circuitInfo
- Publication number
- JPS59187271U JPS59187271U JP8015983U JP8015983U JPS59187271U JP S59187271 U JPS59187271 U JP S59187271U JP 8015983 U JP8015983 U JP 8015983U JP 8015983 U JP8015983 U JP 8015983U JP S59187271 U JPS59187271 U JP S59187271U
- Authority
- JP
- Japan
- Prior art keywords
- input terminal
- circuit
- synchronous separation
- separation circuit
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Synchronizing For Television (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図及び第２図は同期分離回路の従来例を示し、第１
図は回路図、−第２図は波形図、第３図及び第４図は本
考案に係る同期分離回路の実施例を示し、第３図は回路
図、第４図は波形図である。
１・・・差動増幅回路、２・・・一方の入力端、３・・
・他方の入力端、４・・・時定数回路。Figures 1 and 2 show conventional examples of synchronous separation circuits.
2 is a waveform diagram, FIGS. 3 and 4 show an embodiment of the synchronous separation circuit according to the present invention, FIG. 3 is a circuit diagram, and FIG. 4 is a waveform diagram. 1... Differential amplifier circuit, 2... One input terminal, 3...
・The other input terminal, 4... time constant circuit.
Claims (1)
力端が補正信号入力端になっている差動増幅回路と、時
定数回路を持ち上記原信号入力端からの信号を入力とす
るピーク検波回路とを備え、上記ピーク検波回路からの
信号が補正信号きして上記差動増幅回路における他方の
入力端に入力されるように構成されていることを特徴と
する同期分離回路。It has a differential amplifier circuit in which one input terminal is the original signal input terminal and the other input terminal is the correction signal input terminal, and a time constant circuit, and the signal from the above original signal input terminal is input. A synchronous separation circuit comprising a peak detection circuit, and configured such that a signal from the peak detection circuit is inputted to the other input terminal of the differential amplifier circuit with a correction signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8015983U JPS59187271U (en) | 1983-05-30 | 1983-05-30 | Synchronous separation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8015983U JPS59187271U (en) | 1983-05-30 | 1983-05-30 | Synchronous separation circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59187271U true JPS59187271U (en) | 1984-12-12 |
Family
ID=30210151
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8015983U Pending JPS59187271U (en) | 1983-05-30 | 1983-05-30 | Synchronous separation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59187271U (en) |
-
1983
- 1983-05-30 JP JP8015983U patent/JPS59187271U/en active Pending
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