JPS58191770U - Synchronous signal generation circuit - Google Patents
Synchronous signal generation circuitInfo
- Publication number
- JPS58191770U JPS58191770U JP8859482U JP8859482U JPS58191770U JP S58191770 U JPS58191770 U JP S58191770U JP 8859482 U JP8859482 U JP 8859482U JP 8859482 U JP8859482 U JP 8859482U JP S58191770 U JPS58191770 U JP S58191770U
- Authority
- JP
- Japan
- Prior art keywords
- synchronization signal
- input
- circuit
- output
- receives
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Synchronizing For Television (AREA)
- Television Signal Processing For Recording (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の同期信号発生回路の一例を示す図、第２
図はこの考案の一実施例を示すブロック図、第３図ａｘ
ｄ、第４図ａ、 ｂ、第５図ａ、、 ｂはそれぞれ第２
図の動作を説明するためのタイミングチャートである。
２１・・・・・・カウンタ、２２・・・・・・遅延回路
、２３・・・・・・オアゲート回路、２４・・・・・・
論理ゲーＦ’、’３１・・・・・・等化パルス、３２・
・・・・・垂直同期パルス、３３・・・・・・水平同期
信号。Fig. 1 is a diagram showing an example of a conventional synchronization signal generation circuit;
The figure is a block diagram showing one embodiment of this invention.
d, Figure 4 a, b, Figure 5 a, b, respectively.
5 is a timing chart for explaining the operation shown in the figure. 21... Counter, 22... Delay circuit, 23... OR gate circuit, 24...
Logic game F', '31... Equalization pulse, 32.
...Vertical synchronization pulse, 33...Horizontal synchronization signal.
Claims (1)
号を入力とする遅延回路と、複合同期信号と上記遅延回
路の出力とを入力とするオアゲー、 ト回路とを備え
、オアゲート回路の出力をカウンタのクリア端子に入力
すると共に、遅延回路の遅延時間を、オアゲート回路の
両人力の等化パルスおよび水平同期信号が重ならずかつ
垂直同期パルスのみ重なって垂直同期期間にのみオアゲ
ート回路の出力レベルが変動するように設定し、この変
動出力によりクリアされた後のカウンタによる等価パル
スと水平同期信号の計数値に応じてレコードイネーブル
信号を発生するようにしたことを特徴とする同期信号発
生回路。A counter that receives a composite synchronization signal as a counting input, a delay circuit that receives the composite synchronization signal as an input, and an OR gate circuit that receives the composite synchronization signal and the output of the delay circuit as input, and counts the output of the OR gate circuit. At the same time, input the delay time of the delay circuit to the output level of the OR gate circuit only during the vertical synchronization period so that the equalization pulses and horizontal synchronization signals of both of the OR gate circuits do not overlap and only the vertical synchronization pulses overlap. A synchronization signal generation circuit, characterized in that a record enable signal is generated in accordance with the equivalent pulse and the counted value of a horizontal synchronization signal by a counter after being set to fluctuate and cleared by the fluctuating output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8859482U JPS58191770U (en) | 1982-06-14 | 1982-06-14 | Synchronous signal generation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8859482U JPS58191770U (en) | 1982-06-14 | 1982-06-14 | Synchronous signal generation circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58191770U true JPS58191770U (en) | 1983-12-20 |
Family
ID=30097259
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8859482U Pending JPS58191770U (en) | 1982-06-14 | 1982-06-14 | Synchronous signal generation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58191770U (en) |
-
1982
- 1982-06-14 JP JP8859482U patent/JPS58191770U/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| GB1493555A (en) | Decoding circuit for binary data | |
| JPS58191770U (en) | Synchronous signal generation circuit | |
| JPS59180567U (en) | detection circuit | |
| JPS5850755U (en) | Signal disconnection detection circuit | |
| JPS60180139U (en) | counting circuit | |
| JPS5897736U (en) | Tape type identification circuit | |
| JPS60181947U (en) | Receive carrier detection circuit | |
| JPS58538U (en) | Data speed conversion circuit | |
| JPS60135869U (en) | Interleaving RAM read/write pulse generation circuit | |
| JPS58175469U (en) | Phase difference measuring device | |
| JPS60144364U (en) | Video signal delay circuit | |
| JPS6020695U (en) | Input signal detection circuit | |
| JPS6079834U (en) | Clock pulse detection circuit | |
| JPS59159200U (en) | Step motor drive circuit | |
| JPS6045578U (en) | Detection circuit for horizontal, vertical and field signals of TV composite sync signal | |
| JPS60124170U (en) | Video signal processing device | |
| JPS5928863U (en) | Ready circuit of magnetic disk device | |
| JPS58132475U (en) | H-blanking circuit in printer | |
| JPS58169732U (en) | Noise prevention circuit | |
| JPS59180527U (en) | constant pulse width signal generator | |
| JPS6135443U (en) | Pulse output control circuit | |
| JPS5950596U (en) | Pulse motor drive circuit | |
| JPS5978735U (en) | Signal abnormality detection circuit | |
| JPS5834451U (en) | Signal sending circuit | |
| JPS5967040U (en) | Pulse generation circuit |