JPS5967040U

JPS5967040U - Pulse generation circuit

Info

Publication number: JPS5967040U
Application number: JP16291182U
Authority: JP
Inventors: 須藤　敏雄
Original assignee: 日本電気株式会社
Priority date: 1982-10-27
Filing date: 1982-10-27
Publication date: 1984-05-07

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例を示す回狼路ブロック図、第
２図は第１図の動作を説明するための各　、部の波形図
、第３図及び第４図はデユーティ−の変化を示す図であ
る。同図において、１・・・微分回路、２・・・カウンタ、
３・・・一致回路、４・・・アップダウンカウンタ、５
・・・アンドゲート、６・・・出力端子、ａ・・・アン
ドゲートへの入力信号、ｂ・・・微分回路への入力信号
、Ｃ・・・アップダウンカウンタのクロック人カヘメ入
力信　　　□号、ｄ・・・微分回路の出力信号、ｅ・・
・アンドゲートの出力信号、ｆ・・・一致回路及び出力
端子の出力信　−号。゛［− ３１一−Ｂ　　　　　　　　　　−−ｒ６　　　／　　　２　　３　　４　　　ｊ’　　　６　
　７　　　Ｂ−一昨岨醇）第３図 υＰ１０ｏｗｒＪ　ｔｊ梗えFig. 1 is a circuit block diagram showing an embodiment of the present invention, Fig. 2 is a waveform diagram of each section to explain the operation of Fig. 1, and Figs. It is a figure showing a change. In the same figure, 1... Differential circuit, 2... Counter,
3... Matching circuit, 4... Up/down counter, 5
...And gate, 6...Output terminal, a...Input signal to AND gate, b...Input signal to differential circuit, C...Up/down counter clock input signal □No. , d...output signal of the differentiating circuit, e...
- Output signal of AND gate, f...output signal of matching circuit and output terminal - signal.゛[- 31 1-B --r 6 / 2 3 4 j' 6
7 B-Ichiyoshi) Fig. 3 υP10owrJ tj stem

Claims

[Scope of utility model registration request]

an up/down counter for counting up or down; a counter for counting clock pulses; a coincidence circuit for detecting a point of coincidence between an output value of the counter and an output value of the up/down counter; and a logic circuit for controlling the supply of clock pulses to the counter according to an output signal. The counter counts clock pulses input through the logic circuit, and when the output value of the counter matches the output value of the up/down counter, the coincidence circuit generates a coincidence signal, and the coincidence signal causes the logic circuit to When the counter becomes non-conductive, the supply of clock pulses to the counter is stopped, and when the next clear signal is input to the counter, the above operation is repeated. From +1, from the input time of the clear signal to the counter, the The time interval until the matching signal is output from the matching circuit is determined by the output value of the up-down counter, and the output value of the up-down counter increases or decreases with time, and the time interval also increases or decreases accordingly. Pulse generation circuit.