JPS60129747U - Pulse generation circuit - Google Patents

Pulse generation circuit

Info

Publication number
JPS60129747U
JPS60129747U JP1711484U JP1711484U JPS60129747U JP S60129747 U JPS60129747 U JP S60129747U JP 1711484 U JP1711484 U JP 1711484U JP 1711484 U JP1711484 U JP 1711484U JP S60129747 U JPS60129747 U JP S60129747U
Authority
JP
Japan
Prior art keywords
period
counter
pulse
generation circuit
pulse generation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1711484U
Other languages
Japanese (ja)
Inventor
功 高橋
Original Assignee
三洋電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三洋電機株式会社 filed Critical 三洋電機株式会社
Priority to JP1711484U priority Critical patent/JPS60129747U/en
Publication of JPS60129747U publication Critical patent/JPS60129747U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来例を示すブロック図、第2図は本考案の実
施例を示すグロック図、第3図は第2図に示された実施
例の詳細な回路図、第4図は第3図に示された回路図の
動作を示すタイミング図である。
FIG. 1 is a block diagram showing a conventional example, FIG. 2 is a block diagram showing an embodiment of the present invention, FIG. 3 is a detailed circuit diagram of the embodiment shown in FIG. FIG. 3 is a timing diagram showing the operation of the circuit diagram shown in the figure.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 出力するべきパルスの周期が設定されるNビットの周期
設定レジスタと、クロックパルスの印加によって計数を
行うNビットのカウンタと、該カウンタがオーバーフロ
ーしたときに出力されるキャリーによつそ前記周期設定
レジスタに設定されたデータを前記カウンタに印加する
プリセット回路と、前記カウンタのキャリーを1/2分
周するフリップフロップとを備え、前記周期設定レジス
タに設定された値から前記キャリーが発生するまでの期
間の2倍を周期とするパルスを発生するこ−とを特徴と
する発生回路。、
An N-bit period setting register in which the period of the pulse to be output is set, an N-bit counter that counts by applying a clock pulse, and the period setting according to the carry output when the counter overflows. It includes a preset circuit that applies data set in the register to the counter, and a flip-flop that divides the carry of the counter by 1/2. A generating circuit characterized in that it generates a pulse having a period twice as long as the period. ,
JP1711484U 1984-02-08 1984-02-08 Pulse generation circuit Pending JPS60129747U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1711484U JPS60129747U (en) 1984-02-08 1984-02-08 Pulse generation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1711484U JPS60129747U (en) 1984-02-08 1984-02-08 Pulse generation circuit

Publications (1)

Publication Number Publication Date
JPS60129747U true JPS60129747U (en) 1985-08-30

Family

ID=30504518

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1711484U Pending JPS60129747U (en) 1984-02-08 1984-02-08 Pulse generation circuit

Country Status (1)

Country Link
JP (1) JPS60129747U (en)

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