JPS6134481U

JPS6134481U - electronic speedometer

Info

Publication number: JPS6134481U
Application number: JP11971084U
Authority: JP
Inventors: 育夫勝又
Original assignee: カルソニックカンセイ株式会社
Priority date: 1984-08-03
Filing date: 1984-08-03
Publication date: 1986-03-03
Also published as: JPH0329749Y2

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図はこの考案の一実施例を示す電子式速度計の回路
を示すブロック構成図、第２図は従来の電子式速度計の
回路を示すブロック構成図、第３図は第２図タイミング
制御回路の出力波形図である。１・・・車速センサ、２・・・波形整形回路、３・・・
タ、イミング制御回路、４，１３・・・アンドゲート、
５・・・カウンタ、６・・・ラッチ回路、−７・・・デ
コーダ・ドライバ、８・・・表示器、９，１ｏ・・・第
１及び第２のラツチ回路、１１・・・加算回路、１２・
・・ディジタルコンパレータ。Fig. 1 is a block diagram showing a circuit of an electronic speedometer showing an embodiment of this invention, Fig. 2 is a block diagram showing a circuit of a conventional electronic speedometer, and Fig. 3 is a timing diagram of Fig. 2. FIG. 3 is an output waveform diagram of the control circuit. 1... Vehicle speed sensor, 2... Waveform shaping circuit, 3...
timing control circuit, 4, 13...and gate,
5... Counter, 6... Latch circuit, -7... Decoder/driver, 8... Display, 9, 1o... First and second latch circuit, 11... Adder circuit , 12・
...Digital comparator.

Claims

[Scope of utility model registration request]

A counter 5 that inputs vehicle speed pulses generated in proportion to vehicle speed and counts the number of pulses within a predetermined sampling time, and a plurality of latch circuits 9 and 10 that store a plurality of outputs of the counter 5 in time series. and the plurality of latch circuits 9
. An electronic system characterized by comprising a control circuit 12 and 13 that forcibly sets the memory contents of the plurality of latch circuits 9 and 10 to zero when the output reaches a value corresponding to approximately zero vehicle speed. speedometer.