JPS59180527U - constant pulse width signal generator - Google Patents
constant pulse width signal generatorInfo
- Publication number
- JPS59180527U JPS59180527U JP7520983U JP7520983U JPS59180527U JP S59180527 U JPS59180527 U JP S59180527U JP 7520983 U JP7520983 U JP 7520983U JP 7520983 U JP7520983 U JP 7520983U JP S59180527 U JPS59180527 U JP S59180527U
- Authority
- JP
- Japan
- Prior art keywords
- output
- terminal
- flip
- circuit
- pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Pulse Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のもののブロック線図、第２図はその波形
説明図、第３図は本考案の実施例を示すブロック線図、
第４図はその波形説明図である。
１：入力端、２：波形整形回路、３：基準時間パルス発
生器、８：１／ｎカウンタ、９．１１：フリップフロッ
プ回路、１２：アンドゲート回路、１３：出力取出端。FIG. 1 is a block diagram of the conventional one, FIG. 2 is an explanatory diagram of its waveforms, and FIG. 3 is a block diagram showing an embodiment of the present invention.
FIG. 4 is an explanatory diagram of the waveform. 1: Input end, 2: Waveform shaping circuit, 3: Reference time pulse generator, 8: 1/n counter, 9.11: Flip-flop circuit, 12: AND gate circuit, 13: Output extraction end.
Claims (1)
を有する基準時間パルスと同期させた周期パルス信号を
発生させる波形整形回路と、その周期パルス信号がリセ
ット端に、基準時間パルスが計数入力端に導入され、基
準時間パルスのｎカウントごとに周期的に変化する計数
出力を発生するｌ／ｎカウンタ（ｎは所定の整数）と、
前記周期パルスがリセット端に、計数出力がクロック端
に導入されると共に、Ｄセット端を常時高レベルに保持
させた第１のフリップフロップ回路と、−そのＱ出力が
Ｄセット端に、前記計数出力がクロック端に、前記周期
パルスがリセット端にそれぞれ導入される第２のフリッ
プフロップ回路と、第１のフリップフロップ回路のＱ出
力と第２のフリップフロップ回路の回出力とが導入され
るアンドゲート回路とからなるところの定パルス幅信号
発生器。A waveform shaping circuit that generates a periodic pulse signal synchronized with a reference time pulse having a frequency sufficiently higher than that frequency for each period of the input signal, and the periodic pulse signal is connected to the reset terminal and the reference time pulse is connected to the counting input terminal. an l/n counter (n is a predetermined integer) that is introduced and generates a count output that changes periodically every n counts of the reference time pulse;
a first flip-flop circuit in which the periodic pulse is introduced into the reset terminal, the counting output is introduced into the clock terminal, and the D set terminal is kept at a high level at all times; - its Q output is introduced into the D set terminal; a second flip-flop circuit in which the output is introduced into the clock terminal and the periodic pulse is introduced into the reset terminal; and an AND circuit in which the Q output of the first flip-flop circuit and the output of the second flip-flop circuit are introduced. A constant pulse width signal generator consisting of a gate circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7520983U JPS59180527U (en) | 1983-05-19 | 1983-05-19 | constant pulse width signal generator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7520983U JPS59180527U (en) | 1983-05-19 | 1983-05-19 | constant pulse width signal generator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59180527U true JPS59180527U (en) | 1984-12-03 |
| JPH0311952Y2 JPH0311952Y2 (en) | 1991-03-22 |
Family
ID=30205283
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7520983U Granted JPS59180527U (en) | 1983-05-19 | 1983-05-19 | constant pulse width signal generator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59180527U (en) |
-
1983
- 1983-05-19 JP JP7520983U patent/JPS59180527U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0311952Y2 (en) | 1991-03-22 |
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