JPS60135869U

JPS60135869U - Interleaving RAM read/write pulse generation circuit

Info

Publication number: JPS60135869U
Application number: JP2318584U
Authority: JP
Inventors: 哲史糸井
Original assignee: 日本電気ホームエレクトロニクス株式会社
Priority date: 1984-02-21
Filing date: 1984-02-21
Publication date: 1985-09-09

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図および第２図は本考案の背景の説明図、第３図は
本考案の実施例の回路図、第４図は第３図の回路の主要
個所の信号のタイミングチャートである。１３．１４・・・・・・カウンタ制御回路、１５・・・
・・・第１カウンタ、１７・・・・・・第２カウンタ、
１８・・・・・・ＮＡＮＤ回路、ＣＫ３２・・・・・・
入力クロック信号、ＣＫ２４・・・・・・出力クロック
信号、Ａ３・・・・・・基本信号、ＡＩＯ・・・・・・
読出しパルス信号、Ａｌｌ・・・・・・書込みパルス信
号、Ａ１２・・・・・・所要の処理をするためのパルス
信号。1 and 2 are explanatory diagrams of the background of the present invention, FIG. 3 is a circuit diagram of an embodiment of the present invention, and FIG. 4 is a timing chart of signals at the main parts of the circuit of FIG. 3. 13.14... Counter control circuit, 15...
...first counter, 17...second counter,
18...NAND circuit, CK32...
Input clock signal, CK24... Output clock signal, A3... Basic signal, AIO...
Read pulse signal, All...Write pulse signal, A12...Pulse signal for performing required processing.

Claims

[Claims for Utility Model Registration] In a PCM recording and reproducing device that once stores input data in a RAM using an input clock signal, performs necessary processing, and then outputs it using an output clock signal that is asynchronous with the input clock signal, A signal, the output clock signal, and a basic signal having synchronization approximately equal to the access time of one word of the RAM are input, and counting is started at the falling edge of the output clock signal when the input clock signal is at a high level. generates a pulse signal representing one cycle of the basic signal corresponding to a count of 1;
a first counter that outputs a read pulse signal as a read pulse signal; a counter control circuit that generates a control signal that forcibly resets the counter to zero immediately after an output from a counter tube of the first counter; Detects that the count is zero, starts counting at the falling edge of the input clock signal, generates a pulse signal representing one cycle of the basic signal corresponding to count 2, and outputs it as a write pulse signal for the RAM. 2 counters, and NAND of the outputs of the first and second counters.
1. A read/write pulse generation circuit for an interleaving RAM, characterized in that the circuit comprises a NAND circuit that calculates the value of the pulse signal and outputs it as a pulse signal for necessary processing of the RAM.