JPS59192755U - Elastic store circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

Figure 1 shows the conventional elastic store circuit diagram; Figure 2 shows the conventional elastic store circuit diagram;
4 is a circuit diagram of an elastic store according to the present invention, FIG. 3 is a circuit diagram of an embodiment of the present invention, and FIG. 4 is a time chart explaining the operation of FIG. WC...Write clock, WR...Write address reset signal, IN...Input data, RC...Read clock, RR...Read address reset signal.
OUT...Output data, 30...Comparison circuit, 101
゜201...INV gate, 102,202...A
ND gate.

Claims (1)

[Scope of utility model registration request] In an elastic store circuit that sequentially writes input data to memory in synchronization with a write clock, and outputs the contents of the memory sequentially in synchronization with a read clock independently of the write operation, the write address reset signal and the next A circuit that detects whether the number of "1"s in the input data between the write address reset signal and the next read address reset signal is an odd number or an even number, and the output data "1" between the read address reset signal and the next read address reset signal. An elastic store circuit comprising: a circuit for detecting whether the number of " is an odd number or an even number; and a circuit for comparing the results of the two circuits.