JPS58163095U - Defect processing circuit - Google Patents
Defect processing circuitInfo
- Publication number
- JPS58163095U JPS58163095U JP5834982U JP5834982U JPS58163095U JP S58163095 U JPS58163095 U JP S58163095U JP 5834982 U JP5834982 U JP 5834982U JP 5834982 U JP5834982 U JP 5834982U JP S58163095 U JPS58163095 U JP S58163095U
- Authority
- JP
- Japan
- Prior art keywords
- memory
- read
- information
- processing circuit
- defect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の欠陥処理回路のブロック図、第２図は第
１図の欠陥処理回路の動作説明するための図、第３図は
本考案の一実施例に係る欠陥処理回路のブロック図であ
る。
１・・・・・・リードオンリメモリ、２・・・・・・レ
ジスタ、３・・・・・・磁気バブルメモリ、４及び５・
・・・・・ＡＮＤ回路、６・・・・・・書き込み／読み
出しクロック入力端子、７・・・・・・書き込みデータ
入力端子、８・・・・・・読み出しデータ出力端子、９
・・・・・・リードオンリメモリ出力信号線、１０・・
・・・・レジスタデータ入出力クロック信号線、１１・
・・・・・バブルメモリ書き込み信号線、１２・・・・
・・バブルメモリ読み出し信号線、１３・・・・・・反
転回路。FIG. 1 is a block diagram of a conventional defect processing circuit, FIG. 2 is a diagram for explaining the operation of the defect processing circuit of FIG. 1, and FIG. 3 is a block diagram of a defect processing circuit according to an embodiment of the present invention. It is. 1...Read-only memory, 2...Register, 3...Magnetic bubble memory, 4 and 5...
...AND circuit, 6...Write/read clock input terminal, 7...Write data input terminal, 8...Read data output terminal, 9
...Read-only memory output signal line, 10...
...Register data input/output clock signal line, 11.
...Bubble memory write signal line, 12...
...Bubble memory read signal line, 13...Inversion circuit.
Claims (1)
リードオンリメモリを備え、該リードオンリメモリは、
一度、情報“１゛を書き込むと、その情報を“Ｏ“に変
更することができないメモリであり、該リードオンリメ
モリには前記欠陥情報が°゛１“とじて、前記非欠陥情
報が“°０゛とじて記憶されており、該リードオンリメ
モリより読み出された情報に基いて、前記磁気バフルメ
モリへのデータの書き込み及び該磁気バブルメモリから
のデータの読み出しを制御するようにしたことを特徴と
する欠陥処理回路。A read-only memory is provided for storing defect information and non-defect information of the magnetic bubble memory, and the read-only memory includes:
Once the information "1" is written, the information cannot be changed to "O" in this memory, and the defect information is "1" and the non-defect information is "°" in the read-only memory. 0'', and the writing of data to the magnetic baffle memory and the reading of data from the magnetic bubble memory are controlled based on the information read from the read-only memory. defect processing circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5834982U JPS58163095U (en) | 1982-04-23 | 1982-04-23 | Defect processing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5834982U JPS58163095U (en) | 1982-04-23 | 1982-04-23 | Defect processing circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58163095U true JPS58163095U (en) | 1983-10-29 |
Family
ID=30068742
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5834982U Pending JPS58163095U (en) | 1982-04-23 | 1982-04-23 | Defect processing circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58163095U (en) |
-
1982
- 1982-04-23 JP JP5834982U patent/JPS58163095U/en active Pending
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