JPH05236521A - Tone detecting circuit - Google Patents

Abstract

PURPOSE:To detect a tone without erroneous detection due to the noise for the occurrence of lightning surge in the digital subscriber line transmission system of the echo canceller system. CONSTITUTION:A reception signal is sampled in a sampler 103 by 80kHz and is converted to a digital value by a comparator 104. The converted binary digital value is inputted to delay devices 105 to 111 and is delayed by 1 to 7 sample times, and outputs are inputted to a frequency detector 112 consisting of a four-input NAND circuit 13, a four-input NOR circuit 114, a two-input AND circuit 115, and a high level detection counter 116, thereby detecting a tone signal of 10kHz.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is used in a digital subscriber line transmission system using an echo canceller system,
In particular, it relates to the tone detection circuit.

[0002]

2. Description of the Related Art As shown in FIG. 4, a conventional tone detector includes a band pass filter 203, a folding circuit 204, a low pass filter 205, and a comparator 206.

The analog reception signal propagating through the subscriber line 201 and passing through the hybrid circuit 202 is input to the band pass filter 203. In the digital subscriber line transmission system using the echo canceller system, a signal of 10 kHz is defined as a tone signal, and therefore the center frequency of the bandpass filter 203 is 10 kHz. The 10 kHz signal component detected by the bandpass filter 203 is input to the folding circuit 204 and full-wave rectified.
This full-wave rectified signal is converted into a DC signal component by the low pass filter 205. Low pass filter 20
The DC signal component detected in 5 is input to the comparator 206 and compared with a predetermined threshold voltage Vth to detect a tone signal.

[0004]

Since this conventional tone detection circuit detects the power of the 10 kHz component contained in the analog received signal, even if there is a signal other than the original tone, it does not even include the 10 kHz component. If there is, there is a disadvantage that it is mistakenly detected as a tone signal. For example, when a signal waveform as shown in FIG. 5 is added as a received signal when a lightning surge occurs, the 10 kHz component included in this signal causes a false detection as a tone signal.

It is an object of the present invention to provide a tone detection circuit which eliminates the above-mentioned drawbacks so as not to be erroneously detected by noise when a lightning surge occurs.

[0006]

SUMMARY OF THE INVENTION The present invention provides a tone detection circuit having means for detecting a tone signal from a reception signal of an echo canceller type inputted from a subscriber line through a hybrid circuit. A sampling device for sampling with a predetermined sampling signal, a comparator for comparing an output signal of the sampling device with a predetermined threshold voltage and converting it into a binary digital signal, and an output signal from the comparator are inputted. First to seventh delay devices for respectively delaying 1 to 7 sample times, and a frequency for inputting the output signals of the comparator and the output signals of the first to seventh delay devices to detect the tone signal. And a detector.

According to the present invention, the frequency detector is provided with a first AND circuit which receives the output signals of the comparator and the first, second and third delay units to obtain a logical product, and The output signals of the fourth, fifth, sixth and seventh delay devices are inputted and a negative logical sum circuit for taking a negative logical sum, and the output signals of the first logical product circuit and the negative logical sum circuit are inputted. A second logical product circuit that obtains a logical product and an output signal of the second logical product circuit is latched for each sampling period, and when the latched output signal is continuously at a "high" level for a predetermined number of times, the tone signal is output. A level detection counter for outputting as a signal can be included.

According to the present invention, the sampling signal has a frequency of 80 kHz and the tone signal has a frequency of 10 kHz.
It is preferably Hz.

[0009]

The tone signal is constituted by transmitting +3 signal four times at the transmission rate of 80 kHz, then continuously transmitting -3 four times, and this is one cycle for 10 times, that is, 3 ms.

Therefore, the tone signal is converted into a binary (0, 1) digital signal by the sampler and the comparator, delayed by 1 to 7 sample times by the first to seventh delay units, and output with 0 delay. To the third delay device output, the fourth to seventh delay device outputs are ORed together, and both outputs are ORed, the output becomes "1"("high") level. As a result, one cycle of the tone signal is detected. Therefore, when this is detected 10 times in succession, the tone signal is correctly detected.

By the way, if noise due to lightning surge is input in the middle of the process, the outputs of the fourth to seventh delay devices become "0", and "high" level detection cannot be performed. Therefore, this is prevented. It becomes possible.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

This embodiment is a feature of the present invention in a tone detection circuit provided with means for detecting a tone signal from a received signal a of the echo canceller system which is inputted from the subscriber line 101 through the hybrid circuit 102. However, a sampler 103 that samples the received signal a with a sampling signal of 80 kHz, and an output signal of the sampler 103 is compared with a predetermined threshold voltage and converted into a binary (0, 1) digital signal. A comparator 104 which outputs as an output signal b, and first to seventh delay devices 105 to which the output signal b from the comparator 104 is inputted and which delays 1 sample time to 7 sample times, respectively.
111, the output signal of the comparator 104 and the delay device 10
The frequency detector 112 receives the output signals of 5 to 111 and detects the tone signal.

The frequency detector 112 is the comparator 1
04 signal b and first, second and third delay 1
The first AND circuit 113 for inputting the output signals c to e of 05 to 107 and performing the logical product, and the output signals f to of the fourth, fifth, sixth and seventh delay devices 108 to 111 A NOR circuit 114 that receives i and takes the NOR
And a second AND circuit 115 that inputs the output signal j of the first AND circuit 113 and the output signal k of the NOR circuit 114 to obtain a logical product, and the output signal 1 of the second AND circuit 115 Output signal l
When it is at the "high"("1") level 10 times in succession, the high level detection counter 116 outputs the tone signal as the tone signal.

Next, the operation of this embodiment will be described with reference to the timing chart shown in FIG.

In the North American standard digital subscriber line transmission system, the transmission rate is 80 kHz, the transmission line code is ± 1,
A 2B1Q code consisting of four values of ± 3 is used, and as a tone signal, a signal of 10 kHz is created by alternation of ± 3 signals as shown in a reception signal a (showing a tone signal) in FIG. That is, the +3 signal is transmitted at a transmission rate of 80k.
After being transmitted 4 times at Hz, the -3 signal is transmitted 4 times, and this is continuously performed 10 times, that is, for 3 msec, thereby forming a tone signal.

FIGS. 3A and 3B show tone waveform diagrams obtained by simulation. The figure (a) is
It is a tone waveform diagram when the subscriber line is 0 m, that is, when it is directly connected. The figure (b) is a subscriber line 7 km (wire diameter 0.5 m
It is a tone waveform diagram in the case of m). Although there is a difference in voltage level, it can be seen that the received waveform is almost a sine wave in both cases.

The received signal a that has passed through the subscriber line 101 and the hybrid circuit 102 is input to the sampler 103, and
It is sampled at 0HKz. The sampled signal is input to the comparator 104, and the output signal b converted into a binary value (digital value) of "1" and "0" is output depending on whether the signal is positive or negative.

Then, the output signal b is input to the first to seventh delay devices 105 to 111, and 80 k respectively.
There is a delay of 1 sample, 2 samples, 3 samples, 4 samples, 5 samples, 6 samples, and 7 sample times for the sampling of Hzk.

An AND circuit 1 inside the frequency detector 112.
Reference numeral 13 is a 4-input AND circuit that receives the output signal b of the comparator 104 and the output signals c to e of the delay device 107 from the delay device 105, and all four inputs are “1” (high level).
Only when is output "1". Also, the NOR circuit 114
Is a four-input NOR circuit that receives the output signals f to i of the delay device 111 from the delay device 108, and outputs “1” when all four inputs are “0” (low level). The AND circuit 115 is a two-input AND circuit that receives the outputs of the AND circuit 113 and the NOR circuit 114, and outputs "1" only when both inputs are "1".

Therefore, the AND circuit 115 outputs "1" only when the inputs of the AND circuit 113 are all "1" and the inputs of the NOR circuit 114 are all "0". Considering that the sampling frequency is 80 kHz, this corresponds to a period of 10 kHz. That is,
When the output of the AND circuit 115 is "1", 10 kHz
This means that the z signal has been input. The high-level detection counter 116 latches the output of the AND circuit 115 at every 80 kHz, detects a “1” output, and further counts this by 10 to detect a 10 kHz tone signal.

[0023]

As described above, the present invention is 10 k
By performing the Hz detection, there is an effect that the tone signal can be stably detected without being erroneously detected by noise or the like when a lightning surge occurs.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation.

FIG. 3 is a tone waveform diagram obtained by simulation.

FIG. 4 is a block diagram showing a conventional example.

FIG. 5 is a noise waveform diagram added as a reception signal when lightning occurs.

[Explanation of symbols]

 101, 201 Subscriber line 102, 202 Hybrid circuit 103 Sampler 104, 206 Comparator 105-111 Delay device 112 Frequency detector 113, 115 Logical product (AND) circuit 114 NOR gate circuit 116 High-level detection count Device 203 Pass band filter 204 Folding circuit 205 Low pass filter a Received signal b Output signal c (of comparator 104) c Output signal d (of delay device 105) d (Output of delay device 106) e (of delay device 107) Output signal f Output signal of delay device 108 g Output signal of delay device 109 Output signal h of delay device 110 Output signal i of delay device 111 Output signal j of AND circuit 113 Output signal k of NOR circuit Output signal of circuit 114 l Output signal of AND circuit 115

Claims (3)

[Claims] 1. A tone detection circuit comprising means for detecting a tone signal from a received signal of an echo canceller type inputted from a subscriber line through a hybrid circuit, wherein the received signal is sampled by a predetermined sampling signal. The sampler and the output signal of this sampler are compared with a predetermined threshold voltage.
A comparator for converting the value into a digital signal, first to seventh delay units for inputting the output signal from the comparator and delaying each by 1 sample time to 7 sample times, and an output signal of the comparator, And a frequency detector for receiving the output signals of the first to seventh delay devices and detecting the tone signal. 2. The frequency detector receives the output signals of the comparator and the first, second, and third delay devices to perform a logical product, and a first logical product circuit, and the fourth and fourth logical product circuits. Five,
A negative OR circuit that inputs the output signals of the sixth and seventh delay devices and performs a NOR, and a second AND circuit that inputs the output signals of the first AND circuit and the NOR circuit And the output signal of the second AND circuit for each sampling period, and when the latched output signal is at the "high" level for a predetermined number of times in succession, this level detection is output as the tone signal. The tone detection circuit according to claim 1, further comprising a counter. 3. The frequency of the sampling signal is 80k
3. The tone detection circuit according to claim 1, wherein the tone signal has a frequency of 10 kHz and a frequency of 10 kHz.