KR960027637A - Synchronous Signal Detection Device - Google Patents

Synchronous Signal Detection Device Download PDF

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Publication number
KR960027637A
KR960027637A KR1019940036270A KR19940036270A KR960027637A KR 960027637 A KR960027637 A KR 960027637A KR 1019940036270 A KR1019940036270 A KR 1019940036270A KR 19940036270 A KR19940036270 A KR 19940036270A KR 960027637 A KR960027637 A KR 960027637A
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South Korea
Prior art keywords
signal
synchronous signal
error
synchronous
output
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KR1019940036270A
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Korean (ko)
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KR0136048B1 (en
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오재술
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구자홍
Lg 전자주식회사
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0054—Detection of the synchronisation error by features other than the received signal transition

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

본 발명은 직렬 고속 비트 스트림(Serial High Bit Stream) 데이타내의 동기신호 검출장치에 관한 것으로서, 종래 동기검출기는 데이타 스트림에서 동기신호를 검출하여 서로 다른 동기신호가 입력될때 동기신호의 에러 발생에 의해 데이타의오류를 발생하는 경우가 있어 안정된 동기신호를 출력하지 못하는 문제점이 있었다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for detecting a synchronization signal in serial high bit stream data, and a conventional synchronization detector detects a synchronization signal from a data stream and generates data by generating an error of the synchronization signal when different synchronization signals are input. There is a problem that can not output a stable synchronization signal because there is a case of error.

따라서, 본 발명은 이와같은 종래 문제점을 해결하기 위해 유럽방식의 위성방송에서 전송되는 서로 다른 동기신호를 동시에 검출하여 에러 유무를 판별하면서, 안정된 동기신호를 검출하여 에러 발생시 이를 보상하여 안정된 동기신호가 출력되는 동기신호 검출장치이다.Therefore, in order to solve such a conventional problem, the present invention simultaneously detects different synchronization signals transmitted from satellite broadcasts in Europe and determines whether there is an error, and detects a stable synchronization signal and compensates for an error. The synchronization signal detection device is output.

Description

동기신호 검출장치Synchronous Signal Detection Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 3도는 본 발명 동기신호 검출장치의 블록 구성도, 제 4도는 본 발명 동기신호 검출방법을 보인 플로우챠트.3 is a block diagram of the synchronization signal detecting apparatus of the present invention, and FIG. 4 is a flowchart showing the method of detecting the synchronization signal of the present invention.

Claims (3)

입력되는 데이타의 동기신호를 비교하는 동기신호 비교부(10)와, 상기 동기신호 비교부(10)에서 출력된 동기신호로부터 동기신호를 검출하는 동기신호 검출부(11)와, 상기 동기신호 비교부(10)에서 출력되는 동기신호 데이타의에러를 검출하는 제 1동기신호 에러 검출부(12)와, 상기 동기신호 검출부(11)에서 출력되는 동기신호 데이타의 에러를 검출하는 제 2동기신호 에러 검출부(13)와, 상기 제 1 및 제 2동기신호 에러 검출부(12)(13)에서 검출된 에러신호를 동기신호 비교부(10)에 리세트시키기 위한 OR게이트(Gate)(14)와, 상기 입력되는 데이타의 동기신호를 변환시키는 데이타 변환부(15)로 구성된 동기신호 검출장치.A synchronization signal comparison unit 10 for comparing the synchronization signal of the input data, a synchronization signal detection unit 11 for detecting the synchronization signal from the synchronization signal output from the synchronization signal comparison unit 10, and the synchronization signal comparison unit A first synchronous signal error detection unit 12 for detecting an error of the synchronization signal data output from (10), and a second synchronous signal error detection unit for detecting an error of the synchronization signal data output from the synchronous signal detection unit 11 ( 13) OR gates 14 for resetting the error signals detected by the first and second synchronous signal error detectors 12 and 13 to the synchronous signal comparator 10, and the inputs. A synchronization signal detection device comprising a data converter (15) for converting a synchronization signal of data to be converted. 제 1항에 있어서, 동기신호 비교부(10)는 입력되는 데이타의 서로 다른 동기신호를 각각 비교하는 제 1 및제 2동기신호 비교기(16)(17)와, 상기 제 1 및 제 2동기신호 비교기(16)(17)로부터 동기신호를 분리하여 검출하는 제 1동기신호 검출기(18)와, 상기 제 1동기신호 검출기(18)에서 분리되어 출력된 동기신호 데이타를 이용하여 윈도우 펄스를 만드는 윈도우 카운터(19)와, 상기 제 1동기신호 검출기(18)에서 분리되어 출력된 동기신호와 윈도우 카운터(19)에서 출력된 동기신호를 비교하는 제 3동기신호 비교기(20)로 구성되며, 상기 동기신호 검출부(11)는 동기신호 비교부(10)의 제 3동기신호 비교기(20)에서 출력된 동기신호를 분리하여 검출하는 제 2동기신호 검출기(21)와, 상기 제 2동기신호 검출기(21)에서 분리되어 출력된 동기신호를 이용하여 일정한 주기로 카운터시키는 동기신호 카운터기(22)와, 상기 제 2동기신호 검출기(21)에서 분리되어 출력된 동기신호가 비트(Bit) 신호일 경우 바이트(Byte) 신호로 변환시키는 동기신호 변환기(23)와, 상기 동기신호 변환기(23)에서 출력된 동기신호와 동기신호 카운터기(22)에서 출력된 동기신호를 비교하는 제 4동기신호 비교기(24)와, 상기 제 4동기신호 비교기(24)에서 비교되어 출력된 동기신호의 에러가 없을때 동기신호를 검출하는 제 3동기신호 검출기(25)로 구성된 것을 특징으로 하는 동기신호 검출장치.2. The synchronizing signal comparator 10 according to claim 1, wherein the synchronizing signal comparator 10 includes first and second synchronizing signal comparators 16 and 17 for comparing different synchronizing signals of input data, respectively, and the first and second synchronizing signal comparators. (16) A window counter for generating a window pulse by using the first synchronous signal detector 18 for separating and detecting the synchronous signal from the 17 and the synchronous signal data separated and output from the first synchronous signal detector 18. And a third synchronous signal comparator 20 for comparing the synchronous signal output from the first synchronous signal detector 18 with the synchronous signal output from the window counter 19. The detection unit 11 includes a second synchronous signal detector 21 for separating and detecting a synchronous signal output from the third synchronous signal comparator 20 of the synchronous signal comparator 10, and the second synchronous signal detector 21. By using the synchronization signal output separately from the And a synchronization signal converter 23 for converting the synchronization signal counter 22 and the synchronization signal output from the second synchronization signal detector 21 into a byte signal when the output signal is a bit signal. The fourth synchronous signal comparator 24 comparing the synchronous signal output from the synchronous signal converter 23 and the synchronous signal output from the synchronous signal counter 22 and the fourth synchronous signal comparator 24 are compared and output. And a third synchronous signal detector (25) for detecting the synchronous signal when there is no error in the synchronous signal. 제 1항에 있어서, 제 1동기신호 에러 검출부(12)는 입력되는 데이타 스트림에서 초기에 동기신호 데이타가에러일 경우 리세트시키기 위한 제 1동기신호 에러 검출기(26) 및 제 1동기신호 에러 카운터기(27)로 구성되며, 상기 제2동기신호 에러 검출부(13)는 제 4동기신호 비교기(24)에서 출력된 동기신호 중 에러가 발생할 경우 동기신호 에러를 검출하는 제 2동기신호 에러 검출기(28)와, 상기 제 2동기신호 에러 검출기(28)에서 발생되어 출력된 에러의 갯수를 검출하는 제 2동기신호 에러 카운터기(29)와, 상기 동기신호 검출부(11)의 동기신호 카운터기(22)에서 출력된 동기신호를 이용하여 일정구간안에 제 2동기신호 에러 검출기(28)를 리세트시키는 동기신호 펄스 검출기(30) 및 동기신호 펄스 카운터기(31)로 구성된 것을 특징으로 하는 동기신호 검출장치.2. The first synchronous signal error detector (12) according to claim 1, wherein the first synchronous signal error detector (12) is configured to reset the first synchronous signal error detector (26) and the first synchronous signal error counter to reset when the synchronous signal data is initially error in the input data stream. And a second synchronous signal error detector 13 for detecting a synchronous signal error when an error occurs among the synchronous signals output from the fourth synchronous signal comparator 24. ), A second synchronous signal error counter 29 for detecting the number of errors generated and output by the second synchronous signal error detector 28, and a synchronous signal counter 22 of the synchronous signal detector 11 And a synchronizing signal pulse detector (30) and a synchronizing signal pulse counter (31) for resetting the second synchronizing signal error detector (28) within a predetermined period by using the output synchronizing signal. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940036270A 1994-12-23 1994-12-23 Synchronization signal detecting system KR0136048B1 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100859807B1 (en) * 2004-09-23 2008-09-24 삼성전자주식회사 Apparatus and method for providing the clock signal
KR101307101B1 (en) * 2008-11-05 2013-09-11 쟈인 에레쿠토로닉스 가부시키가이샤 Transmission device, receiving device and communication system
KR101631800B1 (en) * 2015-06-25 2016-06-17 인하대학교 산학협력단 Method and Apparatus for Multi-hop Clock Synchronization Based on Robust Reference Node Selection for SANET

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100859807B1 (en) * 2004-09-23 2008-09-24 삼성전자주식회사 Apparatus and method for providing the clock signal
KR101307101B1 (en) * 2008-11-05 2013-09-11 쟈인 에레쿠토로닉스 가부시키가이샤 Transmission device, receiving device and communication system
KR101631800B1 (en) * 2015-06-25 2016-06-17 인하대학교 산학협력단 Method and Apparatus for Multi-hop Clock Synchronization Based on Robust Reference Node Selection for SANET

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