KR870006739A - Frame Sync Detection Method and Circuit - Google Patents

Frame Sync Detection Method and Circuit Download PDF

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Publication number
KR870006739A
KR870006739A KR1019850009608A KR850009608A KR870006739A KR 870006739 A KR870006739 A KR 870006739A KR 1019850009608 A KR1019850009608 A KR 1019850009608A KR 850009608 A KR850009608 A KR 850009608A KR 870006739 A KR870006739 A KR 870006739A
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South Korea
Prior art keywords
state
search
pattern
clock
circuit
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KR1019850009608A
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Korean (ko)
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KR890001178B1 (en
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이진우
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강진구
삼성반도체통신 주식회사
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Priority to KR1019850009608A priority Critical patent/KR890001178B1/en
Publication of KR870006739A publication Critical patent/KR870006739A/en
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Publication of KR890001178B1 publication Critical patent/KR890001178B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B14/00—Transmission systems not characterised by the medium used for transmission
    • H04B14/02—Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation
    • H04B14/04—Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation using pulse code modulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

내용 없음.No content.

Description

프레임 동기 검출 방법 및 회로Frame Sync Detection Method and Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 따른 프레임 동기회로의 도면.1 is a diagram of a frame synchronization circuit according to the present invention.

제2도는 본 발명에 따른 방법을 나타내는 상태변환도2 is a state transition diagram representing a method according to the present invention.

제3(A)도는 본 발명에 따른 동기 검색상태에서 정상 동작상태의 변환을 나타낸 제1도의 각 부분의 파형도.3 (A) is a waveform diagram of each part of FIG. 1 showing the conversion of the normal operation state from the synchronous search state according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 동기패턴 비교회로 2 : 상태변환부1: Synchronization pattern comparison circuit 2: State conversion unit

3 : 클럭제어부 4 : 카운터3: clock control unit 4: counter

10 : 직병렬변환기 12 : 동기패턴 발생회로10: serial and parallel converter 12: synchronization pattern generating circuit

14 : 동기패턴비교기 20 : 제 1래치회로14: synchronous pattern comparator 20: first latch circuit

22 : 제 2래치회로22: second latch circuit

Claims (4)

프레임 동기검출방법에 있어서, 수신데이터를 동기 패턴과 비교하여 불일치할 때는 상기 수신데이터가 동기 패턴과 일치할 때까지 동기 검색상태를 유지하는 제1단계와, 상기 수신데이터가 동기 패턴과 일치하면 동기가 잡힌 상태로 판단하여 동기검색을 중단하며 1프레임 경과후 다시 상기 수신데이터가 동기패턴과 일치하지 않을 때는 제1단계의 동기 검색상태로 가고 일치하면 정상동작상태로 가는 제2단계와, 상기 정상동작 상태에서 1프레임 경과후 수신체이터가 동기패턴과 일치할 때는 정상동작상태를 유지하는 제3단계와, 상기 정상동작상태에서 수신데이터가 동기 패턴과 일치하지 않을 때에는 검색대기 상태로 가고 검색대기 상태에서 1프레임 경과후 상기 수신데이터가 동기 패턴과 일치하지 않을 때는 상기 제1단계로 가고 일치할 때는 정상동작상태로 가는 제4단계로 구성됨을 특징으로 하는 방법.A frame synchronization detection method, comprising: a first step of maintaining a synchronous search state until the received data matches the sync pattern when the received data is inconsistent with the sync pattern; and synchronizing if the received data matches the sync pattern Stops the synchronous search after determining that the state is set to the second state. If the received data does not match the synchronous pattern again after one frame, the synchronous search state goes to the first stage. When the receiver agrees with the synchronization pattern after one frame has elapsed in the operating state, the third step of maintaining the normal operation state; and when the received data does not match the synchronization pattern in the normal operation state, the receiver enters the search standby state and waits for the search. When the received data does not match the synchronization pattern after one frame has elapsed, go to the first step. Method characterized by consisting of a fourth step of going to the operation state. 프레임 동기 검출회로에 있어서, 수신데이터와 동기 패턴을 매비트마다 비교하는 동기 패턴 비교회로(1)와, 상기 동기 패턴 비교회로(1)의 비교논리출력과 상태변환(CLKF)에 따라 동기 검색상태와 검색중지상태와 정상동작상태와 검색대기상태를 구별하여 출력하는 상태변환부(2)와, 상기 상태변환부(2)에서 출력하는 상태신호와 상기 동기 패턴 비교회로(1)의 출력신호()와 캐리신호()와 기준클럭()를 입력하여 상태변환클럭(CLKF)과 카운터의 클리어신호()를 발생하여 상기 상태의 변환을 도모하여 카운트 초기화를 시키는 제어클럭을 발생하는 클럭제어부(3)와, 상기 클리어신호()를 입력하여 1프레임의 소정의 비트를 카운트하면 캐리신호를 발생하고 프레임동기신호를 출력하는 카운터(4)로 구성됨을 특징으로 하는 회로.In the frame sync detection circuit, a sync pattern search circuit 1 for comparing received data with a sync pattern every bit, and a sync search state in accordance with the comparison logic output and state transition (CLKF) of the sync pattern compare circuit 1. And a state conversion unit 2 for discriminating and outputting a search stop state, a normal operation state, and a search standby state, a state signal output from the state conversion unit 2, and an output signal of the synchronous pattern comparison circuit 1; ) And carry signals ( ) And reference clock ( ) To clear the state transition clock (CLKF) and the counter clear signal ( And a clock control unit 3 for generating a control clock for converting the state to initialize the count, and the clear signal ( And a counter (4) for generating a carry signal and outputting a frame synchronization signal when a predetermined bit of one frame is counted. 제2항에 있어서, 상태변환부(2)가 각 상태를 나타내는 신호를 출력하는 제1래치회로(2)와 제2래치회로(22) 및 게이트회로(16)(18)를 구비하여 동기 패턴 비교출력을 상태 변환클럭(CLKF)에 따라 상태변환출력을 상기 제 1 래치회로(20)와 제 2래치회로(22)에서 출력함을 특징으로 하는 회로.3. The synchronization pattern according to claim 2, wherein the state converting section (2) comprises a first latch circuit (2), a second latch circuit (22), and a gate circuit (16) (18) for outputting a signal representing each state. And a comparison output is output by the first latch circuit (20) and the second latch circuit (22) according to the state conversion clock (CLKF). 제2항에 있어서, 클럭제어부(3)가 상태변환부(2)의 출력상태에 따라 정해지는 동기 검색상태(S1)에서는 상태변환클럭(CLKF)이 기준클럭()이 되게 출력하며 카운트 클리어신호()를 출력하며 카운터(4)를 클리어하며 동기 검색상태(S1)이외의 상태에서는 캐리신호()가 입력할 때만 상태변환클럭(CLKF)으로 기준클럭()이 출력하게 하며 클리어신호()가 출력하여 카운터(4)를 초기화하는상태변환클럭(CLKF)과 클리어신호()를 출력하는 논리게이트(24)(26)(28)(30)(32)로 구성됨을 특징으로 하는 회로.3. In the synchronous retrieval state S 1 according to claim 2, wherein the clock control section 3 is determined according to the output state of the state transition section 2, the state transition clock CLKF is the reference clock. ) And the count clear signal ( ) And an output carry signal in a state other than and clears the counter (4) the synchronization search state (S 1) ( Only when is input by the state transition clock (CLKF) ) Outputs a clear signal ( Is outputted to initialize the counter (4) and the clear signal ( And a logic gate (24) (26) (28) (30) (32) for outputting ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019850009608A 1985-12-19 1985-12-19 Frame synchronizing detecting method and circuit KR890001178B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019850009608A KR890001178B1 (en) 1985-12-19 1985-12-19 Frame synchronizing detecting method and circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019850009608A KR890001178B1 (en) 1985-12-19 1985-12-19 Frame synchronizing detecting method and circuit

Publications (2)

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KR870006739A true KR870006739A (en) 1987-07-14
KR890001178B1 KR890001178B1 (en) 1989-04-26

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KR1019850009608A KR890001178B1 (en) 1985-12-19 1985-12-19 Frame synchronizing detecting method and circuit

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