JPS601785B2 - Count comparison detection circuit for synchronous counter circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a counter number comparison and detection circuit for a synchronous counter circuit that compares and detects coincidence between a count number of a counter circuit and a preset count number.

When it is necessary to know that the count number of the counter circuit has reached a preset count number, a comparison detection circuit is used that constantly compares the count number of the counter circuit and the preset count number.

FIG. 1 shows, as an example of a counter circuit, a conventional counter number comparison and detection circuit of a synchronous type octal binary counter circuit, which compares and detects coincidence of count numbers of a synchronous type octal binary counter circuit.

In FIG. 1, reference numeral 1 denotes a 1-bit shift circuit 2, which is composed of a clock inverter lc and an inverter 1 as shown in FIG. 2, and whose operation is controlled by a clock pulse and its complement pulse. This is a synchronous octal binary counter circuit with a multi-stage configuration, which includes various gate circuits inserted between the 1-bit shift circuits and forming an adder circuit. That is, a one-stage counter is composed of a 1-bit shift circuit 2 and an adder circuit, and each adder circuit receives the carry output of the previous stage and the output of the 1-bit shift circuit 2 of the corresponding stage. It forms an addition output for input to the 1-bit shift circuit 2, and also forms a carry output for the next stage. The synchronous octal binary counter circuit 1 counts the supplied clock pulses and sequentially counts bits 2 and 2 as shown in FIG.
Count output signals Q, .about.Q of 0 to 22 are output. On the other hand, in FIG. 1, 3 is the count output signal Q, ~Q, and bit data L set in advance.
This is a comparison detection circuit for performing coincidence comparison detection with each of D and LD3 to obtain coincidence signals E and Q. For example, when each of the bit data LD, ~LD3 is at the "1" level,
That is, when comparing and detecting that the count number of the counter circuit 1 has reached "7", the count output signal Q
,~When all Qs reach “1” level, Noah Gate 4,~
The output level of each of the NOR gates 4 and 43 becomes a "0" level, and the output level of the NOR gate 5, in which the outputs of the NOR gates 4 and 43 are connected in parallel, becomes a "1" level. As a result, a coincidence signal of "1" level is established in the output signals E and Q of the NOR gate 5, and it is recognized that the count number of the counter 1 has reached the preset count number. However, in the above circuit, the count output signal Q
,~The signal lines 6,~63 through which false signals are transmitted have stray capacitances C,
.about.C3 are present, the comparison detection circuit 3 receives the count output signal Q. There will be a slight delay in reaching ~Q3.

Further, since the values of the stray capacitances C and .about.C3 differ depending on the signal lines 6 and .about.63, their delay times also differ. Now, the count output signals Q, ~Q3, which take into account the delay time reaching the comparison detection circuit 3, are converted to Q, '~Q, respectively.
3' and clock pulse? If the delay times for the rise of are respectively t·, t2, etc. as shown in FIG. 4, each of the signals Q,' to Q3' will be at the "1" level during the period to. As a result, Noah Gate 5
In this period, a "1" level coincidence signal is established. In this way, in the counter number comparison detection circuit of the conventional synchronous counter circuit, due to the influence of stray capacitance, a match signal is established even if the count number of the counter circuit and the preset count number do not match, resulting in malfunction. It has the disadvantage of causing

This invention was made in consideration of the above-mentioned circumstances, and its purpose is to provide a synchronous counter circuit that is not affected by the stray capacitance of the signal lines through which the count output of the counter circuit is transmitted and does not cause malfunctions. An object of the present invention is to provide a counter number comparison detection circuit.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 5 shows an example of the use of the comparison and detection circuit of the present invention. Here, as in the conventional case, the comparison and detection of the number of counters of a synchronous counter circuit is carried out to compare and detect the coincidence of the counts of a synchronous octal binary counter circuit. The case of a circuit will be explained. In FIG. 5, 11 indicates a signal q, in which the data supplied to the data input terminal D, is shifted by a half bit of this clock pulse 0, and a signal Q, which is shifted by 1 bit, in accordance with the smallness of the supplied clock pulse. The output signal Q of this shift circuit 11 is fed back to the data input terminal D through an inverter 12. Furthermore, the above signal Q, is the OR gate 13 and the NAND gate 1.
4 in parallel. The output signal of the NAND gate 14 is supplied to an OR gate 15 and a NAND gate 16, respectively.

The output signal of the NAND gate 14 is also supplied to an AND gate 17 together with the output signal of the OR gate 13, and the output signal of the AND gate 17 is further supplied to a data input terminal D2 of a shift circuit 18. Similar to the shift circuit 11, this shift circuit 18 outputs a signal q2 shifted by half a bit and a signal Q2 shifted by 1 bit in response to the clock pulse ◇' of the data supplied to the data input terminal ○2. It is supposed to be done. The signal Q2 output from the shift circuit 18 is supplied to the OR gate 13 and the NAND gate 14, respectively. The respective output signals of the OR gate 15 and the NAND gate 16 are both supplied to an AND gate 19. Furthermore, the output signal of this AND gate 19 is supplied to a data input terminal D3 of a shift circuit 20. This shift circuit 2
Similarly to the shift circuits 11 and 18, 0 clock pulses the data supplied to the data input terminal D3. Accordingly, a signal q3 shifted by half a bit and a signal Q3 shifted by 1 bit are output, respectively. The signal Q3 outputted from the shift circuit 20 is applied to the OR gate 1.
5 and NAND gate 16, respectively. The shift circuits 11, 18, 20, OR gates 13, 15
, NAND gates 14, 16, AND gates 17, 19, and inverter 2 constitute a synchronous octal binary counter circuit 21 that sequentially counts supplied clock pulses ◇.
The signals Q, , Q2, and Q output from the shift circuits 11, 18, and 20 respectively correspond to bits 20 to 20.
23 count output signals. In addition, each signal q
, , q2, and q3 are signals that are half bits ahead of the signals Q, , Q2, and Q3, respectively. That is, in the above-described synchronous octal binary counter circuit 21, one stage of the counter includes OR gates 13 and 15 and NAND gates 14 and 1, respectively.
6 and AND gates 17 and 19, respectively, and shift circuits 18 and 20, each of which is supplied with the addition output of each addition circuit as an input, and these counters are connected in multiple stages.

Each adder circuit is fed with the 1-bit shift output of the shift circuit of the counter in that stage and the carry output of the previous stage counter as input, and the outputs of NAND gates 14 and 16 are used as carry outputs, and the outputs of AND gates 17 and 19 are fed as inputs. The output is set to addition output. A signal q output from the shift circuit 11 is supplied in parallel to an AND gate 32 and a NOR gate 33 via a signal line 31.

Both the AND gate 32 and the NOAH gate 33 have the following:
Preset bit data LD, which is compared and detected for coincidence with signal q, is supplied. Furthermore, and gate 3
The output signals of NOR gate 2 and NOR gate 33 are supplied to NOR gate 34 in parallel.

The signal q2 output from the shift circuit 18 is supplied to an AND gate 36 and a NOR gate 37 in parallel via a signal line 35. And gate 36 above
Both of the NOR gates 37 and 37 are supplied with preset bit data LD2 for comparing and detecting coincidence with the signal q2. Furthermore, AND Gate 36 and Noah Gate 3
The output signals of 7 are supplied to the NOR gate 38 in parallel. Furthermore, the signal q3 output from the shift circuit 20 is supplied to an AND gate 40 and a NOR gate 41 in parallel via a signal line 39. Both the AND gate 40 and the NOR gate 41 contain preset bit data LD3 for comparing and detecting coincidence with the signal q3.
is supplied. Furthermore, the Noah gates 34, 38,
42 respective output signals are supplied to /Agate 43 in parallel. The AND gates 32, 36, 40 and the NOR gates 33, 34, 37, 38, 41, 42, 4
3 is a count output signal Q of each of bits 20 to 22 outputted from the synchronous octal binary counter circuit 21;
~ Count output signal q before each half-bit shift of Q3, ~
A comparison circuit 44 that compares q3 with bit data LD, LD3 corresponding to preset bits 2o to 22, respectively, determines whether count output signals q, q3 and bit data LD, LD3 match each other. When this happens, a coincidence signal of "1" level is established in the output signals E and Q of the NOR gate 43. In addition, each signal line 3
1, 35, and 39 have stray capacitances C and ~C with different values, respectively.
3 exists. The output signal of the NOR gate 43 is supplied to a so-called clocked inverter 45, which is a clocked gate circuit that performs an inversion operation only during the period when the clock pulse generator is established. Furthermore, the output signal of this clocked inverter 45 is supplied to an inverter 46. The output signal of this inverter 46 is also the clock pulse? The output signal of the clocked inverter 47 is fed back to the input terminal of the inverter 46. The output signal of the clocked inverter 47 is fed back to the input terminal of the inverter . The clocked inverters 45, 47 and the inverter constitute a half-bit shift circuit 48 for the signals E, Q, and the inverter 46 outputs a half-bit shift signal E, which is obtained by shifting the signals E, Q by half a bit. Q and S are output. Also, this half bit shift circuit 4
8 and the comparison circuit 44 constitute a comparison detection circuit. Note that the inverter 4 in the half-bit shift circuit 48
6 and clocked inverter 47 constitute a stable circuit that stably maintains the output of clock inverter 45, and inverter 46 and clocked inverter 47 can be omitted.

FIG. 6 shows the shift circuits 11, 18, and 20 in detail, and the data is the complementary pulse of the clock pulse ◇
It is connected to a clocked inverter 51 which performs an inverting operation only during the period when .

The output signal of this clocked inverter 61 is supplied to an inverter 52, and the output signal of this inverter 52 is further supplied in parallel to clock inverters 53 and 54 which perform an inverting operation only during the period when the clock pulse J is established. . The output signal of the one clock inverter 53 is fed back to the input device of the inverter 52. Further, the output signal of the other clock inverter 54 is supplied to an inverter 55. In addition, this inbar evening 5
The output signal of 5 is output from a clock diverter 56 which performs an inversion operation only during the establishment period of the complementary pulse of the smaller clock pulse.
is supplied to. The output signal of this clocked inverter 56 is fed back to the input terminal of the inverter 55. The data supplied from the inverter 52 to the clocked inverter 51 is a clock pulse? A signal q shifted by a half bit is outputted, and a signal Q obtained by further shifting the signal q by a half bit is outputted from the inverter 55.
Next, the operation of the circuit configured as described above will be explained using the timing chart shown in FIG.

First, when the count number of the synchronous octal binary counter circuit 21 that performs coincidence detection in the comparison detection circuit is set to a full count of "7", the bit data LD, ~L
D3 are each set to the "1" level. Next, the counter circuit 21 and the half-bit shift circuit 48 receive a low clock pulse and a complementary pulse of this pulse? Enter each. The count output signal q of the shift circuit 11 is synchronized with the falling edge after the 0th pulse of the clock pulse is established.
, rises to the "1" level as shown in FIG.
Then, after the first pulse of the clock pulse J is established, in synchronization with the fall of the first pulse, the count output signal q again falls to the "0" level as shown in FIG. Subsequently, the count output signal q2 of the shift circuit 18 rises to the "1" level.Furthermore, after the second pulse of the clock pulse ◇ is established, in synchronization with the fall of the second pulse, the count output signal q, rises to the "1" level. As shown in Figure 7, “
Further, after the third pulse of the clock pulse ◇ is established, in synchronization with the fall of the third pulse, the count output signal q falls to the "0" level as shown in FIG. Following this, the count output signal q2 is also “0”
rise to the level. Furthermore, following the falling of the count output signal q2, the count output signal q3 rises to the "1" level. By the way, the count output signals q, ~q3 are connected to the stray capacitances C, ~C present in each signal line 31, 35, 39.
Considering that each clock pulse is delayed by 3? When the third pulse is established, and then near the trailing edge, there is a period in which both the q and -q ports are at the "1" level, as in the conventional case. As mentioned above, the bit data LD, ~
Since the LD3 is each at the "1" level, the output signals of the AND gates 32, 36, and 40 are all at the "1" level, and the output signals of the NOR gates 33, 37, and 41 are both at the "0" level. The output signals of 34, 38, and 42 are at the "0" level. As a result, as shown in FIG. 7, the output signals E and Q of the NOR gate 43 are at the "1" level near the falling edge of the third pulse of the least clock pulse. Thereafter, the count output signals Q, .about.Q representing the actual count of the counter circuit 21, which are shifted by a half bit from the count output signals q, .about.q3, respectively, become "0" as shown in FIG. level, “0” level, and “1” level. Above count output signal Q, ~Q
corresponds to the count number "4", indicating that the count is not yet full. Next, during the fourth period of the clock pulse, the clock inverter 45 following the NOR gate 43 reads the output signals E and Q of the NOR gate 43. Since the signals E and Q are already at the "0" level during the fourth pulse formation period, the output signals 1 and E of the clock diverter 45 are
, Q remain at the "1" level as shown in FIG. As a result, the subsequent output signal E of the inverter 46
, Q, and S remain at the "0" level as shown in FIG. 7, and even if the output signals E, Q of the NOR gate 43 reach the "1" level, no coincidence signal is established. More clock pulses? Even in the vicinity of the falling edge after the formation of the 5th and 11th pulses, there is a period in which both q and q3 are at the "1" level, and the output signals E and Q of the NOR gate 43 are as shown in FIG. However, the signals E and Q are already at the "0" level during the period when the 6th and 12th clock pulses are low, which is the reading timing of the clock inverter 45, as described above. It becomes.
Therefore, in this case as well, the output signals 1, E, and Q of the clocked inverter 45 remain at the "1" level as shown in FIG. As shown in the figure, it remains at the "0" level. That is, in this case as well, a coincidence signal is not established. Next, after the sixth pulse of the clock pulse q is established, the count output signal q,
rises to the “1” level.

At this time, as shown in FIG.
, q3 are already at the "1" level. Thereafter, the count output signals Q and -Q representing the actual count of the counter circuit 21, which are shifted by a half bit from each of the count output signals q and -q3, are all "1" as shown in FIG. level. That is, the count output signals Q, .about.Q correspond to the count number "7", which indicates a full count state. The signal q,
〜q3 are both at “1” level, each AND gate 3
The output signals of NOR gates 2, 36, and 40 are at "1" level, and the output signals of each NOR gate 33, 37, and 41 are at "0" level.
Furthermore, the output signals of the NOR gates 34, 38, and 42 are all “
As a result, as shown in FIG. 7, the output signals E and Q of the NOR gate 43 become "1" level during the period when q is established.Next, during the period when the seventh pulse of the clock pulser is established, Then, the clock diverter 45 following the NOR gate 43 reads the output signals E and Q of the NOR gate 43. At this time, the period during which the signals E and Q are established lasts for one bit of the clock pulse pulse, so the clock diverter 45 follows the NOR gate 43. The output signals 1, E, and Q of the inverter 45 fall to the "0" level as shown in FIG. The clocked inverter 47 inverts the output signal of the inverter 46. As a result, during the "0" level period of the clock pulse ? that follows after the establishment period of the seventh clock pulse ◇, the signal at the input terminal of the inverter 46, that is, the signal 1, E, and Q are at the "0" level as shown in FIG. 7. Therefore, the output signals E, Q, and S of the inverter 46 are the actual count output signals of the counter circuit 21, as shown in FIG. The level is "1" during the period when both Q, ~Q are at the "1" level. That is, in this case, a coincidence signal is established. In this way, the count output signals Q, ~Q representing the number of outputs of the counter circuit 21 are A match signal is established only when Q3 matches the preset bit data LD, ~LD3.This match signal is synchronized with the clock pulse ◇ at the end where the match signal is established, that is, immediately before the inverter 46, that is, at the clocked inverter 43. Therefore, the delay time of the timing of establishment of the clock pulse pulse is also reduced.

Clock pulses supplied like this? The signals q and q3 before the half-bit shift of the count output signals Q and . By shifting the above-mentioned clock pulse by half a bit and not detecting a “1” level signal with a pulse length of less than half a bit of the clock pulse which is established in the above-mentioned comparison signal, the count number is set in advance by bit data. The count number expressed by LD, ~LD3 and 1.
It is possible to provide a counter number comparison and detection circuit for a synchronous counter circuit in which a coincidence signal is established only when the count outputs are matched, and thus does not cause malfunction regardless of the value of the stray capacitance of the signal line through which the count output is transmitted.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a counter number comparison detection circuit of a conventional synchronous counter circuit, FIG. 2 is a detailed diagram of a portion of the slave circuit, and FIGS. 3 and 4 respectively explain the conventional circuit. FIG. 5 is a configuration diagram of one embodiment of the present invention, FIG. 6 is a detailed diagram of a portion of the above embodiment, and FIG. 7 is a timing chart for explaining the above embodiment. 11, 18, 20...shift circuit, 12, 46...
...Inverter, 13,15...Or gate,
14, 16...Nand Gate, 17, 19, 32, 36
, 40...AND gate, 21...Synchronous octal binary counter circuit, 31, 35, 39...
...Signal line, 33, 34, 37, 38, 41, 42
, 43... Noah gate, 44... Comparison circuit, 45, 47... Clock inverter, 48...
Half bit shift circuit, 51, 53, 54, 56. ．．・．．
．． -Clocked inverter, 52, 55...inverter. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7

Claims (1)

[Claims] 1. A one-stage counter has an adder circuit that obtains an adder output and a carry output, and the adder output of this adder circuit is supplied as an input, and shifts the input in half-bit units based on the first and second clock pulses, and performs a one-bit shift. The adder circuit at each stage is supplied with the 1-bit shift output of the 1-bit shift circuit of the counter at that stage and the carry output obtained from the adder circuit of the counter at the previous stage. A synchronous counter circuit consisting of a synchronous counter circuit, a comparison section that compares and detects the match between the half-bit shift output of each of the 1-bit shift circuits and each preset bit data, and the detection output obtained from the comparison section is supplied as an input. a clocked gate circuit controlled by one of the first and second clock pulses, and a shift section that shifts the detection output by a half bit of the clock pulse to generate a coincidence signal; A count number comparison and detection circuit for a synchronous counter circuit, characterized in that the shift section does not generate a coincidence signal when the detection output in the clock pulse is less than a half bit of the clock pulse.