JP3222377B2 - Bit synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to, for example, a method for inputting data transmitted via a transmission line to a digital transmission device or an exchange device in accordance with the timing of the digital transmission device or an exchange device. It relates to a bit synchronization circuit.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing an example of a conventional bit synchronization circuit. The bit synchronization circuit is, for example, a circuit that inputs data transmitted to the switching device in accordance with the timing of the switching device. This bit synchronization circuit includes counters 1 and 3 for generating write and read addresses, a memory 2 for temporarily storing transmitted data, and a most significant digit bit (hereinafter MS) of a read address.
B), decoders 5 and 6 for generating a comparison pulse when the write and read addresses have a preset value, and an AND for detecting address duplication based on the comparison pulse. And a gate 7. This bit synchronization circuit operates as follows.

For example, a clock signal CK1 and data DIN are extracted from transmission data on a transmission path (not shown), and the clock signal CK1 is input to the counter 1 and the data DIN is input to the memory 2. The output terminals QA, QB, QC, and QD of the counter 1 are counted up in synchronization with the rise of the clock signal CK1.
A binary digit is output. The output signal of the counter 1 is used as a write address WAD of the memory 2 as write address terminals WA0, WA1, WA2, and WA of the memory 2.
Given to 3. The memory 2 has a write address terminal WA
Data DIN input to the data input terminal DI is stored in a storage area specified by the write address WAD given to 0 to WA3. On the other hand, a clock signal CK2 having a frequency substantially equal to the frequency of the clock signal CK1 is input to the counter 3 from, for example, an exchange (not shown). The output terminals QA, QB, and QC of the counter 3
A three-digit binary number that is counted up in synchronization with the rising of clock signal CK2 is output. The output signal of the counter 3 is provided to the MSB generator 4. The MSB generation unit 4 generates a fourth digit MSB based on the clock signal CK2 and the output signal of the counter 3. The three-digit binary number output from the counter 3 and the MSB output from the MSB generation unit 4 are applied as read addresses RAD to read address terminals RA0, RA1, RA2, and RA3 of the memory 2. The memory 2 has read address terminals RA0 to RA0.
A storage area specified by read address RAD given to RA3 is read, and output data D is output to data output terminal DO.
Output as OUT.

The write address WAD output from the counter 1 is further applied to input terminals A, B, C and D of the decoder 5. The signal S5 output to the output terminal Q0 of the decoder 5 is activated and becomes “H” level while the input write address WAD is, for example, address 0. The read address RAD output from the counter 3 and the MSB generator 4 is further provided to input terminals A, B, C, and D of the decoder 6. The signal S6 output to the output terminal Q0 of the decoder 6 is, like the decoder 5,
It stays at "H" while the input read address RAD is at address 0. The signals S5 and S6 are ANDed by the AND gate 7, and the result is output to the output side of the AND gate 7 as the overlap signal LAP. This overlap signal LAP
Becomes "H" when the write address WAD and the read address RAD with respect to the memory 2 become the address 0 at the same time. The overlap signal LAP is given to the MSB generation unit 4, and when the overlap signal LAP becomes “H”, the MSB generation unit 4 inverts the MSB output so far (“H” → “H”).
“L” level or “L” → “H”). As a result, it is possible to avoid that the write address WAD and the read address RAD for the memory 2 have the same address at the same time, and accurate memory access is guaranteed. Also,
The overlap signal LAP is displayed / recorded as an alarm signal ALM, and is used for operation management of a switching device or the like.

[0005]

However, the conventional bit synchronization circuit has the following problems. Since the clock signals CK1 and CK2 are provided from the transmission line and the switching device, the frequency and the phase do not always match. Therefore, for example, when the frequency of the clock signal CK1 becomes slightly higher than the frequency of the clock signal CK2, the write address WAD catches up with the read address RAD. Thus, the write address WA
When D catches up with the read address RAD, the operation shown in FIG. 3 is performed. FIG. 3 is a time chart showing the operation of the bit synchronization circuit of FIG. The overlap signal LA of FIG.
P is an output signal of the AND gate 7 in FIG. 2 when the signal S5 output when the write address WAD is at address 0 and the signal S6 output when the read address RAD is at address 0 overlap. . As described above, since the slight frequency shift is detected, the pulse width of the overlap signal LAP becomes extremely narrow, and is called a spike pulse.

[0006] The spike pulse is originally generated by the MSB generator 4.
Is not recognized as a normal signal in the logic circuit. For this reason, whether the MSB generator 4 of FIG. 2 operates with the overlap signal LAP has been unstable and uncertain. The overlap signal LAP is also output as the alarm signal ALM, but the detection of the alarm signal ALM on the receiving side has been uncertain. For this reason, there is a problem that the relationship between the operation of the MSB generation unit 4 and the alarm display does not match. Further, when the bit synchronization circuit of FIG. 2 is manufactured, for example, as an LSI (Large Scale Integrate Circuit), the inspection result in the product inspection varies depending on a slight difference in the pulse width of the spike pulse, and the reproducibility is increased. There was a problem that was bad. An object of the present invention is to provide a bit synchronization circuit which solves the problems of the prior art, that is, the problem of inconsistency between circuit operation and alarm display and the problem of reproducibility during product inspection.

[0007]

According to a first aspect of the present invention, a write address is generated in a fixed order based on a first clock signal synchronized with a first timing. An address generation unit that generates read addresses in the fixed order based on a second clock signal synchronized with timing; and stores data in a storage area specified by the write address in accordance with the first timing; A storage unit that outputs data of the storage area specified by the read address according to the timing of
When the write address reaches a preset value,
A comparison pulse generator that generates a first comparison pulse having a pulse width corresponding to the set value and, when the read address reaches the set value, generates a second comparison pulse having a pulse width corresponding to the set value; A duplication detection unit that detects a duplication state between the write address and the read address and outputs a duplication signal based on the first and second comparison pulses; and, based on the duplication signal, the write address or In a bit synchronization circuit including an address change unit that changes any one of the read addresses, the duplication detection unit is configured as follows.

That is, the overlap detecting section of the first invention comprises a pulse width adjusting section for adjusting a pulse width of the first comparison pulse so as to be longer than a cycle of the second clock signal; A synchronization unit that synchronizes the first comparison pulse adjusted by the width adjustment unit with the second clock signal to generate a third comparison pulse; and a synchronization unit that generates the third comparison pulse. And a detecting unit for detecting an overlapping state of the address and generating an overlapping signal and supplying the overlapping signal to the address changing unit. According to a second aspect, in the same bit synchronization circuit as the first aspect, the duplication detecting section is configured as follows. That is, the duplication detection unit of the second invention,
A pulse width adjustment unit that adjusts a pulse width of the second comparison pulse so as to be longer than a cycle of the first clock signal; and a second comparison pulse adjusted by the pulse width adjustment unit. A synchronizing unit that generates a third comparison pulse in synchronization with the first clock signal, detects an overlap state between the first comparison pulse and the third comparison pulse, generates an overlap signal, and generates the overlap signal. And a detection unit that supplies a signal to the address change unit.

According to the first and second aspects of the present invention, since the bit synchronization circuit is configured as described above, the following operation is performed. When the first and second clock signals are input to the address generator, a write address and a read address are generated in a certain order based on these clock signals. When the write address and the read address reach a preset set value, the comparison pulse generator outputs the first and second comparison pulses that continue while the respective write values are set. The first and second comparison pulses are provided to an overlap detection unit. The pulse width of the first (or second) comparison pulse is adjusted by a pulse width adjustment unit in the overlap detection unit so as to be longer than the cycle of the second (or first) clock signal. The first (or second) comparison pulse having a pulse width longer than the period of the second (or first) clock signal is synchronized with the second (or first) clock signal by the synchronization unit. Then, a third comparison pulse is generated.

An overlapping state between the second (or first) comparison pulse and the third comparison pulse is detected by a detection unit, and an overlap signal indicating the detection result is supplied to the address change unit. When the overlap signal is input to the address change unit, the write address or the read address is changed. When the write address is changed, the changed write address and the unchanged read address are given as a write address and a read address for the storage unit, and data is stored and read according to these addresses.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a configuration diagram of a bit synchronization circuit according to a first embodiment of the present invention. The bit synchronizing circuit, for example, of the clock signal CK1 and the data DIN extracted from transmission data on a transmission path (not shown)
Address generation unit (for example, counter) 1 to which K1 is input
It has 0. The counter 10 receives the clock signal CK1
Output terminals QA, QB, QC, Q
A circuit for counting up a 4-digit binary number output to D. The output side of the counter 10 is connected to the write address terminals WA0, WA1, and WA of the storage unit (for example, memory) 20.
2 and WA3. The memory 20 stores data DIN input to the data input terminal DI in a storage area specified by the write address WAD given to the write address terminals WA0 to WA3. Also,
The memory 20 has read address terminals RA0, RA1, R
The data in the storage area specified by the read address RAD given to A2 and RA3 is output to the data output terminal DO.

The bit synchronization circuit has a counter 30 to which a clock signal CK2 having a frequency substantially equal to the frequency of the clock signal CK1 is input from, for example, a switching device (not shown). The counter 30 outputs the output terminals QA and QA in synchronization with the rising of the clock signal CK2.
This circuit counts up three-digit binary numbers output to B and QC. The output side of the counter 30 is connected to the address changing unit 40. The address changing unit 40 changes the read address RAD by generating the MSB of the read address RAD of the memory 20 and inverting the MSB based on the overlap signal LAP. The address change unit 40 includes a three-input AND gate 41,
It is composed of EOR (exclusive OR) gates 42 and 43 and a flip-flop (FF) 44. The three inputs of the AND gate 41 include a counter 3
0 are connected to each other. The output side of the AND gate 41 is connected to the first input side of the EOR gate 42. The output side of the EOR gate 42 is EO
It is connected to the first input of the R gate 43. Furthermore,
The second input of the EOR gate 43 has an overlap signal LAP
Is entered. The output side of the EOR gate 43 is FF
44. The clock terminal of the FF44
The clock signal CK2 is input, and the output signal of the FF 44 is the MSB. The output side of the FF44 is E
It is connected to the second input side of the OR gate 42.

The output side of the counter 30 and the output side of the FF 44 are connected to read address terminals RA0, RA1,
It is connected to RA2 and RA3, and also to a comparison pulse generator (for example, a decoder) 50. The decoder 50 has input terminals A, B, C, and D, and output terminals Q0,
, Q15, and only the output signal of an output terminal (for example, Q0) corresponding to a 4-bit binary number given to the input terminals A to D is set to "H" level, and the other output terminals At the “L” level. On the other hand, the output side of the counter 10 is connected to the decoder 60. The decoder 60 has the same function as the decoder 50, and its output terminals Q0 and Q1 are connected to the duplication detection unit 70. The overlap detection unit 70 includes a pulse width adjustment unit (for example, an OR gate) 71 and a synchronization unit (for example, F
F) 72, 73, inverter 74, AND gate 75,
And a detection unit (for example, an AND gate) 76.

The input side of the OR gate 71 has a decoder 6
0 output terminals Q0 and Q1 are connected to this decoder 60.
Is connected to the FF 72. The output side of the FF 72 is connected to the FF 73. The clock signal CK2 is input to the clock terminals of the FFs 72 and 73. The output side of the FF 73 is connected to the
D gate 75, and the AND gate 75
The other input side is connected to the output side of the FF 72. The output side of the AND gate 75 is connected to the AND gate 76.
The output of the decoder 50 is connected to the other input of the AND gate 76. The AND gate 76 is a circuit that outputs the overlap signal LAP, and its output side is connected to a second input side of the EOR gate 43 and to an alarm display device (not shown) or the like. FIG. 4 is a time chart showing the operation of the bit synchronization circuit of FIG. Hereinafter, the operation of the bit synchronization circuit of FIG. 1 will be described with reference to FIG.

At time t1, when the clock signal CK1 rises from the "L" level to the "H" level and the output signal of the counter 10, that is, the write address WAD becomes address 0, the output signal is output from the output terminal Q0 of the decoder 60. The comparison pulse CP1 becomes “H”. This comparison pulse CP
Since 1 is input to the OR gate 71, the OR gate 7
The output signal S71 of "1" also becomes "H". This output signal S7
1 is input to the FF 72. At time t2, at the rising of the clock signal CK2, the signal S72 on the output side of the FF72 becomes "H". At the next rise of clock CK1 at time t3, write address WAD output from counter 10 changes to address 1. As a result, the comparison pulse CP1 of the output terminal Q0 of the decoder 60 becomes “L”.
However, since the output signal S60 of the output terminal Q1 becomes “H” instead, the output signal S71 of the OR gate 71 is output.
Maintain the state of “H”.

At time t4, when the clock signal CK2 rises, the input signals of the FFs 72, 73 are at "H" level, so that the signals S72, S72,
S73 both become "H". Output signal S7 of FF72
2 is input to the AND gate 75, and the output signal S73 of the FF 73 is also input to the AND gate 75 via the inverter 74. As a result, the comparison pulse CP3 output from the AND gate 75 becomes “H” during the time t2 to t4 in synchronization with the clock signal CK2. On the other hand, the counter 30 together with the address changing unit 40 sequentially updates and outputs the read address RAD at the time of the rise of the clock signal CK2. Hereinafter, the operation of the address changing unit 40 will be briefly described.

It is now assumed that the read address RAD is at address 15, ie, the output signals of the output terminals QA to QC of the counter 30 and the output signal of the FF 44 are all "H". Further, it is assumed that the overlap signal LAP input to the second input terminal of the EOR gate 43 is “L”. The output signal of the AND gate 41 is “H”, and the EOR gates 42 and 43
Are both "L", the clock signal C
At the next rise of K2, all the output signals of the counter 30 become "L", the output signal of the FF 44 also becomes "L", and the read address RAD becomes address 0. Thus, FF44
When the overlap signal LAP is "L", all the output signals of the counter 30 become "H" and then alternately inverted to generate the MSB of the read address RAD.
However, when the overlap signal LAP becomes “H”, the signal input to the FF 44 is inverted by the EOR gate 43. Therefore, the MSB is forcibly inverted at the next rising of clock signal CK2, and read address RA is read.
D is forcibly changed. Thus, the read address RAD is output from the counter 30 and the address changing unit 40 and input to the decoder 50.

Clock signal CK at time t2 in FIG.
When the read address RAD changes from address 15 to address 0 at the rise of 2, the comparison pulse CP2 output from the output terminal Q0 of the decoder 50 becomes "H". The comparison pulse CP2 becomes “H” while the read address RAD is at the address 0, that is, from time t2 to t4, and is input to the AND gate 76. On the other input side of the AND gate 76, a comparison pulse CP3 output from the AND gate 75 is provided.
Is entered. The two comparison pulses CP1 and CP3 are both “H” during the period from time t2 to time t4. Therefore, the overlap signal LAP output from the AND gate 76
Becomes "H" during the period from time t2 to t4. This overlap signal LAP is sent to the EOR gate 4 of the address change unit 40.
Therefore, when the clock signal CK2 rises at time t4, the MSB of the read address RAD is forcibly changed. Then, the read address RAD is not address 1 but address 9. On the other hand, the write address WAD is 1
Since the address is the address, it is possible to avoid that the write address WAD and the read address RAD become the same address at the same time.

As described above, the bit synchronization circuit of the present embodiment generates the signal S71 by extending the comparison pulse CP1 corresponding to the write address WAD output from the decoder 60 by the OR gate 71 to the period of the signal S60. I have. The signal S71 is synchronized with the clock signal CK2 by the FF 72 to generate the comparison pulse CP3.
Therefore, an accurate overlap signal LAP synchronized with the clock signal CK2 is obtained at the output side of the AND gate 76.
As a result, there is an advantage that a reliable address change operation can be performed by the overlap signal LAP, and an accurate alarm display or the like can be performed by using the overlap signal LAP as the alarm signal ALM.

Second Embodiment FIG. 5 is a block diagram showing a bit synchronization circuit according to a second embodiment of the present invention. Elements common to those in FIG. 1 are denoted by the same reference numerals. . In the bit synchronization circuit of this embodiment, a duplication detection unit 70A having substantially the same function is provided instead of the duplication detection unit 70 of FIG. The duplication detection unit 70A outputs the comparison pulse CP output from the decoder 50.
2 in synchronization with the clock signal CK1 and the comparison pulse CP
3 is provided. Further, the overlap detection unit 70A has a function of detecting an overlap state between the comparison pulse CP3 and the comparison pulse CP1 output from the decoder 60, and outputting an overlap signal LAP. The operation of the bit synchronization circuit shown in FIG.
The point that the pulse width is adjusted based on the AD is different from the bit synchronization circuit of FIG. 1 that performs the pulse width adjustment based on the write address WAD. Other operations of the bit synchronization circuit of FIG. 5 are substantially the same as those of the bit synchronization circuit of FIG.
It has similar advantages. Note that the present invention is not limited to the above embodiment, and various modifications are possible. For example, there are the following modifications.

(A) In the bit synchronization circuit of FIG. 1, the duplication detecting section 70 is provided on the write address WAD side and the address change section 40 is provided on the read address RAD side, but the address change section 40 is provided on the write address WAD side. To
A duplicate detection unit 70 may be provided on the read address RAD side. (B) In the bit synchronization circuit of FIG.
Although the address conversion unit 40 and the duplication detection unit 70A are provided on the D side, the address conversion unit 4 is provided on the write address WAD side.
A zero and overlap detection unit 70A may be provided. (C) In FIG. 1 and FIG. 5, the write address WAD and the read address RAD have a 4-digit configuration. However, if the write and read addresses have the same number of digits, they need not be 4 digits. By increasing the number of digits of the address, the probability that the address will be duplicated is reduced, and stable operation is possible. (D) In FIGS. 1 and 5, the comparison pulses CP1 and CP2
Is output when the write and read addresses are at address 0, but may be output at other addresses. Further, the comparison pulses CP1 and CP2 may be output over a plurality of consecutive addresses. When the comparison pulses CP1 and CP2 are output at consecutive addresses, the overlap state can be detected before the write address WAD and the read address RAD actually overlap, so that overlap can be avoided in advance. (E) The FF 73, the inverter 74, and the AND gate 75 in FIG. 1 may be omitted, and the output side of the FF 72 may be directly connected to the AND gate 76. By doing so, the pulse width of the comparison pulse CP3 input to the AND gate 76 is increased, so that the probability of outputting the overlap signal LAP increases, but the circuit configuration is simplified.

[0022]

As described above in detail, according to the first and second aspects of the invention, the pulse width adjustment unit adjusts the comparison pulse so as to be longer than the cycle of the clock signal. The comparison pulse is synchronized by a clock signal in a synchronization unit. For this reason, the detection unit can reliably detect the overlap state of the comparison pulse, and can output an overlap signal having a regular pulse width. As a result, there is an effect that the address change and the alarm display can be performed reliably. Such an effect eliminates a discrepancy between the address change operation and the alarm display, and furthermore, when this bit synchronization circuit is formed into a product such as an LSI, an additional effect that reproducibility in product inspection is guaranteed. is there.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a bit synchronization circuit according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional bit synchronization circuit.

FIG. 3 is a time chart illustrating an operation of the bit synchronization circuit of FIG. 2;

FIG. 4 is a time chart illustrating an operation of the bit synchronization circuit of FIG. 1;

FIG. 5 is a configuration diagram of a bit synchronization circuit according to a second embodiment of the present invention.

[Explanation of symbols]

 10, 30 counter 20 memory 40 address change unit 50, 60 decoder 70 duplication detection unit CK1, CK2 clock signal LAP duplication signal RAD read address WAD write address

Claims (2)

(57) [Claims] A write address is generated in a fixed order based on a first clock signal synchronized with a first timing, and a read address is generated based on a second clock signal synchronized with a second timing. An address generation unit for generating data in an order; storing data in a storage area specified by the write address according to the first timing; and outputting data in the storage area specified by the read address according to the second timing When the write address reaches a preset value,
A comparison pulse generator that generates a first comparison pulse having a pulse width corresponding to the set value and, when the read address reaches the set value, generates a second comparison pulse having a pulse width corresponding to the set value; Based on the first and second comparison pulses, an overlap detection unit that detects an overlap state between the write address and the read address and outputs an overlap signal; and based on the overlap signal, the write address or A bit synchronization circuit comprising: an address change unit that changes any one of the read addresses; wherein the overlap detection unit sets the pulse width of the first comparison pulse to be greater than the period of the second clock signal. A pulse width adjustment unit that adjusts the pulse width to be longer; and a third comparison pulse generated by synchronizing the first comparison pulse adjusted by the pulse width adjustment unit with the second clock signal. A synchronization unit, and a detection unit that detects an overlap state between the second comparison pulse and the third comparison pulse, generates an overlap signal, and provides the overlap signal to the address change unit. A bit synchronization circuit characterized by the above. 2. A method for generating a write address in a fixed order based on a first clock signal synchronized with a first timing, and changing a read address based on a second clock signal synchronized with a second timing. An address generation unit for generating data in an order; storing data in a storage area specified by the write address according to the first timing; and outputting data in the storage area specified by the read address according to the second timing When the write address reaches a preset value,
A comparison pulse generator that generates a first comparison pulse having a pulse width corresponding to the set value and, when the read address reaches the set value, generates a second comparison pulse having a pulse width corresponding to the set value; Based on the first and second comparison pulses, an overlap detection unit that detects an overlap state between the write address and the read address and outputs an overlap signal; and based on the overlap signal, the write address or A bit synchronization circuit comprising: an address change unit that changes any one of the read addresses; wherein the overlap detection unit sets the pulse width of the second comparison pulse to be greater than the period of the first clock signal. A pulse width adjustment unit that adjusts the pulse width to be longer; and a third comparison pulse generated by synchronizing the second comparison pulse adjusted by the pulse width adjustment unit with the first clock signal. A synchronization unit, and a detection unit that detects an overlap state between the first comparison pulse and the third comparison pulse, generates an overlap signal, and supplies the overlap signal to the address change unit. A bit synchronization circuit characterized by the above.