JP2625908B2 - Jitter absorption selection method for asynchronous elastic stored memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to selection of an amount of jitter absorption in a memory circuit using two elastic stored memories that enable asynchronous and simultaneous reading and writing of data. In order to reduce the chance of data destruction due to collision between data writing and reading by increasing the buffer capacity by increasing the cycle of In the case of performing data speed conversion using an elastic stored memory having redundancy of data storage, control data, a write control signal, and a read control signal are input from an external circuit, and the write control signal and the read control signal are input. Divide the read control signal to the desired cycle and output the write reset signal and read signal And generating two gate signals having the same period and different polarities, which are obtained by dividing the write reset signal by two, and converting the two gate signals and the write reset signal into a first signal.
And a first FF for outputting the two write signals and writing the elastic stored memory, and different polarities of the same period obtained by dividing the read reset signal by two. Are generated, the two gate signals are combined with the write reset signal by a third AND fourth AND, and the two write signals are output to write the elastic stored memory. A second FF is provided, and the control unit sets the frequency division ratio and changes the buffer capacity to select the amount of jitter absorption.

[Industrial applications]

The present invention relates to selection of an amount of jitter absorption in a memory circuit using two elastic stored memories that enable asynchronous and simultaneous reading and writing of data.

In the communication between one ground station and another ground station, especially in data communication via a satellite, a parallel configuration is used as a method to remove the effect of jitter generated on the propagation path in the middle,
In addition, data transmission and reception are performed using an elastic stored memory (hereinafter referred to as ESM), which reduces the influence of jitter by enabling simultaneous writing and reading asynchronously.

In this case, in the control of the ESM in the conventional method, writing and reading are controlled at a constant period, and therefore, the buffer capacity of the ESM is fixed. Originally, the buffer capacity changes due to an external factor (for example, jitter in the propagation path), and the required buffer capacity differs each time. Therefore, when the external factor changes, the same fixed circuit cannot cope with it, and it is desired to provide a circuit having a configuration in which the buffer capacity changes according to the external factor.

[Conventional technology]

 FIG. 4 is a diagram showing the configuration of a conventional example.

1 is the first FF, 2 is the first AND, 3 is the second AND, 4a is the first ESM, 4b is the second ESM, and 5 is the second FF,
6 is a third AND, 7 fourth AND, Note 8 first locking oscillator frequency f _1, 9 is a second clock oscillator frequency f _2.

Here, the first ESM4a or the second ESM4b is a so-called elastic stored memory (hereinafter, referred to as ESM), and one of the memories having two input ports is dedicated to writing and the other is ESM4. One port is dedicated to reading, and even if the input of both ports is asynchronous and the operating speed (frequency) is different, as long as the write and read addresses do not match, elastic data that avoids collisions Is a memory having a parallel two-sided configuration provided to enable writing and reading of data. 4a and 4b
By adopting a parallel configuration, when an abnormality occurs in one memory, for example, when a collision between data writing and reading occurs, the data is stored in another memory.
This is because the reliability of data storage is improved by providing a so-called memory with redundancy.

The first FF1, the first AND2 and the second AND3 are synchronized with the _first clock frequency f1, and the second FF5 and the third AND6
And the fourth NAD 7 operate in synchronization with the _second clock frequency f2. The writing side of the first ESM4a and the second ESM4b operates in synchronization with the _first clock frequency f1, and the opposite reading side operates at the second clock frequency f1.
each f ₂ are synchronized, both clocks are controlled by the phase control loop.

FIG. 5 is a diagram showing write / read timings in the conventional method. FIG. 5 will be described below in conjunction with FIG. As an example of the data configuration, one frame is composed of 24 clocks.

When a 24-clock / 1-frame write reset signal (hereinafter referred to as * WR signal) shown in FIG. 5 (B) is input to the first FF1, a positive and negative repetition gate is set every 48 clocks divided by 2. Output from the terminal Q of the first FF1. While the first
The terminal * Q of FF1 outputs a negative and positive repetition gate having a polarity opposite to the output of the terminal Q. The output from the terminal Q and the * WR signal are combined by the first AND2 to output a write signal 1 (* WR1 signal) shown in (C), which is input every time one write clock (WCLK) is input. Data (Di)
Is written to the first ESM 4a. Similarly, the write signal (* WR2 signal) shown in FIG. 5D is output from the second AND3, and the input data (Di) is written to the second ESM 4b.

FIG. 5A shows the relationship between the writing of the first ESM 4a and the writing of the second ESM 4b. First, when the * WR1 signal is input, the first ESM 4a performs 24-bit writing. Next, the first ESM
When the writing of 4a reaches 24 bits and the writing is completed, the writing of the second ESM 4b starts, and when the writing is completed, the process sequentially proceeds to the writing of the first ESM 4a.

During writing of the first ESM4a or the second ESM4b,
The read reset signal (* RR) is input to the second FF5,
Similarly to the first FF1, the first AND2, and the second AND3, the third A
Operate the ND6 and the fourth AND7 to operate the first ESM4a or the second ESM4a.
It is possible to read from ESM4b. This state is performed as described as the writing of the first ESM 4a or the reading of the second ESM 4b shown in FIG. That is, this reading is performed by the first ESM4a, then the second ESM4a
4b, then move on to the first ESM 4a.

However, in order to avoid a collision when reading from the same first ESM 4a, for example, during writing of the first ESM 4a, the time T as the prohibited area of the first ESM 4a as shown in FIG. ₁ is provided. When in writing the data to the time T _1, must not make a read of the data, also data destruction is caused by performing the reading of data. This area is read for the first ESM4a to consists of two frames and the time T ₂ of the approximately 2 frame minus the time T _1.

Even if of course enter this about 2 frame of time T ₂ to the read-out reset signal (* RR) is, destruction of data can read without. The area where the second ESM4b can be read has a time T _{4 of} about 2 frames as shown in FIG.
Is the time indicated.

During the writing and reading operations as described above, for example, when the data and the first and second clock frequencies fluctuate due to jitter, the writing time and the reading time are fixed values (for example, 2 Frame), it is impossible to secure a constant prohibited area for the first ESM 4a or the second ESM 4b. As a result, fluctuations in jitter increase the chances of collision between writing and reading.

[Problems to be solved by the invention]

Therefore, when reading during writing of the elastic stored memory when the data or the clock frequency fluctuates due to jitter, the chances of data reading collision in both accesses increase.

An object of the present invention is to increase the buffer capacity by increasing the period of reading and writing of the ESM, increase the amount of jitter absorption, and reduce the chance of data destruction due to data collision.

[Means for solving the problem]

 FIG. 1 is a diagram showing the configuration of one embodiment of the present invention.

In the figure, reference numeral 10 denotes a control unit which inputs control data, a write control signal, and a read control signal from an external circuit, and outputs a write reset signal and a read signal divided into a desired cycle, and 1 denotes a 1 FF, and divides the write reset signal by two to generate two gate signals each having the same period and different polarities, and divides the gate signal and the write reset signal into a first AND2 and a second AND2. AND3 combines the two and outputs two write signals to write in the elastic stored memories 4a and 4b. Reference numeral 5 denotes a second FF. Generates two gate signals having the same period and different polarities, and combines the gate signal and the write reset signal in a third AND6 and a fourth AND7 to form two write signals. And performs error stay click stored memory 4a, writing 4b outputs a degree.

The control unit 10 is configured to select the jitter absorption amount by arbitrarily setting the frequency division ratio and variably increasing the buffer capacity.

[Action]

In the present invention, as shown in FIG. 1, control data, a write control signal, and a read control signal are input from an external circuit to a control unit 10, and a write reset signal and a read signal that are divided into a desired cycle are output. So that both signals are
After dividing the frequency of the FF1 and the second FF5 by 2, the first AND2 and the second AND3, and the third AND6 and the fourth AND7 are combined and written into the elastic stored memories 4a and 4b. Or read it out.

Therefore, the jitter absorption amount can be selected by arbitrarily setting the frequency division ratio of the control unit 10 and making the buffer capacity variable.

〔Example〕

 FIG. 1 is a diagram showing the configuration of a conventional example.

1 is the first FF, 2 is the first AND, 3 is the second AND, 4a is the first ESM, 4b is the second ESM, 4a and 4b are of a parallel configuration, and 5 is the second FF, 6 is the third AND, 7 is the fourth A
ND, 10 is a control unit of the present invention. Note first clock oscillator frequency f ₁ of 8 shown in the conventional example of FIG. 4, the second clock oscillator frequency f ₂ of 9 are described omitted.

FIG. 2 is a diagram showing write / read timings in the method of the present invention, and FIG. 3 is a control unit 10 used in the present invention.
FIG. 3 is a diagram showing the configuration of FIG.

Hereinafter, the present invention will be described with reference to FIG. 1, FIG. 2, and FIG.

The control unit 10 in FIG. 1 receives the control data of the “H” level, the write control signal (* WRM) and the read control signal (* RRM), and divides the signal into a desired period from the control unit 10. The reset signal (* WRG) and the read signal (* RRG) are output. (The details of the control unit 10 will be described later with reference to FIG. 3.) The first FF1, the first AND2, and the second AND3 operate in synchronization with the _first clock frequency f1. The second FF5, the third AND6, and the fourth AND7 are connected to the second clock frequency f ₂
It is operating in synchronization with. The first ESM4a and the second ESM
Writing side 4b to the first clock frequency f _1, also read out side, respectively synchronized second clock frequency f ₂ to the operation, that both clocks are controlled by the phase control loop the first 4 is the same as the diagram showing the configuration of one embodiment of the related art.

FIG. 2 is a diagram showing write / read timings in the method of the present invention. As shown in FIG.
A write control signal (hereinafter, referred to as a * WRM signal) and a read control signal (hereinafter, referred to as an * RRM signal), each of which is composed of 24 clocks, are input to the control unit 10 to divide the frequency by 4, and a write reset signal (* WRG) And outputs a reset signal (* RRG) to the first FF1 and the second FF5. Note that the dividing ratio of dividing by 4 can be arbitrarily set in the control unit 10.

In the first FF1, the * WRG signal obtained by dividing the frequency by 4 is further added by 2
The frequency is divided, and as shown in FIG.
A write signal 1 (* WR signal 1) having a negative polarity is output for each frame, and input data is written to the first ESM 4a by a write clock.

Similarly, a write signal (* WR2 signal) shown in FIG. 2D is output from the first AND2 to write the input data (Di) into the second ESM 4b.

The first ESM 4a and the second ESM 4b are written to the first ESM 4a and then to the second ESM 4b as shown in FIG.
Next, the data is sequentially written into the first ESM 4a in 96-bit units. Accordingly, the write buffer capacity in this case is four times as large as that of the conventional 24-bit.

When reading during writing of the first ESM4a or the second ESM4b, the read control signal (* RRG) is set to the second ESM4a or the second ESM4b.
FF5 to operate the third AND6 and the fourth AND7,
Reading from the first ESM 4a or the second ESM 4b is the same as in the conventional example, and the state is shown in FIG. 2 (A). This reading is performed in the order of the first ESM 4a, the second ESM 4b, the first ESM 4a, and so on.

During the writing of the first ESM 4a, the same first
For the avoidance of data collisions when reading from ESM4a, time T ₁ of the as prohibited area of the first ESM4a as shown in FIG. 2 (E) are provided. Must not make a read of the data at the time of writing in the data in this time T _1, also data destruction is caused by performing the reading of data. The same applies to the case of the second ESM4b.

Out area reading this time first ESM4a and second ESM4b is about 8 frames time T ₂ and time T ₄ becomes, the buffer capacity read four times the approximately 2 frames of the conventional example.

FIG. 3 is a diagram showing the configuration of the control unit 10 used in the present invention. In the figure, 101 is an input / output register, 102 to 105 are write-side circuits, 102 is a first counter, 103 is a first INV, 104 is a second INV, and 105 is a first NAND. Reference numerals 106 to 109 denote read-side circuits, 106 denotes a second counter, 107 denotes a third INV, 108 denotes a fourth INV, and 109 denotes a second NAND.

The input / output register 101 receives a signal at the “H” level or the “L” level. 4 when 'H' level signal is input
Bit-structured data is output, and the output is input to terminals A, B, C, and D of the first counter 102 and the second counter 106, respectively. First counter 102 and second counter 106
Are hexadecimal counters.

Now, the operation on the writing side will be described as an example. The output of the input / output register 101 is 1100 (data corresponding to hexadecimal C), and the input terminals A, B, C,
When D loads 1, 1, 0 and 0 respectively, a write signal (* WR) is input to the input terminal CLK of the first counter 102.
M), the input terminal of the first counter 102
From the CO, an output obtained by calculating 16−C = 4, that is, a signal divided by 4 is output, and the divided signal and the * WRM signal via the first INV 103 are synthesized by the first AND 105. And outputs a write reset signal (* WRG) from the first AND 105. The output from the first AND 105 performs a write operation to the first ESM 4a. Also, the second counter on the reading side
The signals generated by the 106, the third INV 107, and the fourth INV 108 are combined by the second NAND 109 to output a read reset signal (* RRG) to read from the first ESM 4a and the second ESM 4b. Performing the dashi is the same as that of the writing side described above.

That is, in the present invention, the control unit 10 is provided to increase the buffer capacity by arbitrarily changing the writing and reading cycles to increase the buffer capacity.
Even if the second clock frequency or the like fluctuates due to jitter, by selecting a period corresponding to the jitter, the buffer capacity is increased to reduce the chance of collision between writing and reading due to fluctuation in jitter. Is what you do.

〔The invention's effect〕

As described above, according to the present invention, the amount of jitter absorption can be increased by making the buffer capacity of the elastic stored memory variable.

As a result, it is possible to set the amount of jitter absorption according to the system.

[Brief description of the drawings]

FIG. 1 is a diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a diagram showing the timing of writing / reading in the method of the present invention, and FIG. 3 is a diagram showing the configuration of a control unit 10 used in the present invention. FIG. 4 is a diagram showing a configuration of a conventional example, and FIG. 5 is a diagram showing write / read timings in a conventional method. In the figure, 1 is the first FF, 2 is the first AND, 3 is the second AND, 4a is the first ESM, 4b is the second ESM, 5 is the second FF, and 6 is the third FF. AN
D and 7 indicate a fourth AND.

Claims (1)

(57) [Claims] 1. An apparatus for performing data speed conversion using an elastic stored memory (4a, 4b) having a parallel two-plane configuration and having data storage redundancy, wherein control data and a write control signal are supplied from an external circuit. And a control unit (10) for inputting a read control signal, dividing the write control signal and the read control signal into desired periods, and outputting a write reset signal and a read signal. The frequency is divided by 2 to generate two gate signals having the same cycle and different polarities, and the two gate signals and the write reset signal are subjected to a first AND operation.
(2) and a second AND (3), and the two write signals are output and the elastic stored memory (4a, 4
b) generating a first FF (1) for performing writing, and generating two gate signals having the same period and different polarities obtained by dividing the read reset signal by 2; Third AND with signal
(6) and a fourth AND (7), and the two write signals are output to generate an elastic stored memory (4a, 4a).
a second FF (7) for writing b) is provided, and the control section (10) sets the frequency division ratio and changes the buffer capacity to select the amount of jitter absorption. Elastic stored memory jitter absorption amount selection method.