JPS5934025B2 - buffer memory circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of configuring a large-capacity elastic buffer memory, particularly an elastic buffer memory used for speed conversion.

For example, by converting the speed of a 1.544 Mb/S digital signal as shown in Figure 1a,
Let us consider the case of converting it into an O48Mb/S digital signal.

Here, it is assumed that the 1.544 Mb/S signal constitutes one frame with 193 bits, the 2.048 Mb/S signal constitutes one frame with 256 bits, and the frame periods of both are the same. Also, the signal conversion rule is 1.544Mb/S
Of the 193 bits constituting one frame of the signal, 192 bits excluding the frame synchronization signal (indicated by F in Figure 1a) are predetermined among the 256 bits constituting one frame of the 2.048 Mb/S signal. Place it in the correct position.
It is assumed that the remaining 64 bits (256 bits to 192 bits) of the 256 bits as above are loaded with a frame synchronization signal of the 2.048 Mb/S signal and others. Also 1.544M
The frame phases of the b/S signal and the 2.048 Mb/S signal generally do not match, and the 1.544 Mb/S signal has a delay variation of about 20 bits (assuming that it has low frequency jitter). As a format conversion procedure, first convert the 1.544Mb/S signal to the accompanying 1.544Mb/S signal.
2.048Mb/S, which specifies the output signal by writing the contents of the memory to the buffer memory using the b/S clock.
It is read out at a predetermined time using a clock. The phase of the write clock and the phase of the read clock constantly fluctuate relative to each other due to differences in their frequencies and variations in input signal delay, so the buffer memory has a function to perform write operations independently of read operations. In other words, an elastic function is required. On the other hand, since the frame phases of both signals do not match, in order to place the input signal at a predetermined position in the output frame, it is necessary to at least
．． One frame of 544Mb/S signal, that is, 193
A capacity of 100 bits is required for the buffer memory. As such a large-capacity memory, so-called random access memory (hereinafter referred to as RAM) is suitable because highly integrated devices exist on the market, but it generally cannot perform writing and reading at the same time. Since the structure is such that elastic operation cannot be performed as it is, it cannot be used for the above purpose. On the other hand, if the circuit is constructed using elements with a small degree of integration, elastic operation becomes possible, but as the memory capacity increases, the circuit scale becomes extremely large. For this reason, conventionally, for example, the memory was divided into two parts,
A method has been used in which an elastic memory made up of elements with a small degree of integration is placed at the front stage to achieve bit phase synchronization, and then a frame phase adjustment memory made up of RAM is placed next. In this case, the elastic memory is capable of handling input signal jitter and 1.544 Mb/S
It must have enough capacity to absorb the equivalent jitter that appears when converting the clock to a 2.048 Mb/S burst clock. In the above example, the scarcity value was 20 to 30 bits, and the circuit size had to be considerably large. SUMMARY OF THE INVENTION An object of the present invention is to provide a means for constructing a large-capacity elastic buffer memory used in the above-mentioned case with three simple circuits.

FIG. 2 is a block diagram showing the structure of the buffer memory of the present invention. In FIG. 2, 21 is a digital signal input terminal, 22 is a three-input terminal for a clock signal whose bit phase is synchronized with the digital signal, and 23 is a clock signal input terminal that determines the bit phase of the output signal of this buffer memory. It is assumed that the clock signal is an input terminal, and its repetition frequency F2 is higher than the repetition frequency f1 of the clock signal input to the terminal 22. Furthermore, 24 is the 2-divided force 4
Counter 25 is a timing circuit which uses the output of 24 as a data input and the clock input to terminal 23 as a trigger input. Furthermore, 26 is a memory having a capacity of 2 bits, which alternately stores input data signals bit by bit under the control of the output of the divide-by-2 counter 24.
It is held for a period of f1. Further, 27 is a selector that selects one of the two outputs of 26 under the control of the output of 25, 28 is a pulse generator that has the function of generating an output at the time when the output signal of the timing circuit 25 changes, and 29 is a selector that selects one of the two outputs of 26. Random access memory circuit (RAM), 210 is a counter that specifies a RAM write address, 211 is a counter that specifies a RAM read address, 212 is an input terminal for a write enable control signal, and 213 is an output terminal of the RAM. FIG. 3 is an example of a specific circuit configuration for a part of the block diagram shown in FIG. 2.

Portions indicated by the same numbers in FIGS. 2 and 3 represent the same contents. Further, FIG. 4 is a timing diagram showing waveforms at various parts in FIG. 3. The operation of the circuit according to the present invention will be explained in detail below with reference to FIGS. 3 and 4. The timing diagrams labeled with letters A, b, c, etc. in FIG. 4 show timing diagrams at positions labeled with the same letters in FIG. 3. In FIG. 4, the frequency of the input clock a is divided by two in a divide-by-two circuit 24,
The outputs are b and c.

Input data d is alternately stored one bit at a time in two memories by b and c to become e and f. Since the repetition frequency of a is f1, the retention time T1 of each bit in e and f is.

On the other hand, the terminal 23 is supplied with a clock g having a repetition frequency F2. Let's say here.

B is timed by g in the timing circuit 25, and becomes h. i is h with phase inversion.
Since the repetition period T2 of g is given as the maximum waiting time until this timing, the following holds true regarding the time T3 until the rising point of b.

The same holds true for the time T4 from the falling point of b to the falling point of h.

Since the time from the rise of b to the fall of b is T1/2, the time from the rise of b to the fall of h is T5.
The relationship holds true.

On the other hand, equations (1), (2), and (3) hold true. Furthermore, equations (6) and (7) hold true (Fig. 5).

Since the data retention period at e was T1 time from the rising edge of b, from equations (4) and (8), the data retention period is wider than the period of selection pulse h, and there is no possibility that the data will change midway. It turns out that this does not occur. This fact is exactly the same for the other data string f,
The input data string is phase-quantized by the clock g and appears at the selector output l without any omissions. In the bit division of the cheetah row l, the level of h is alternately inverted, but h
Waveforms J and h that are delayed by 1/2 bit of the g clock
By taking the exclusive OR with h
It is possible to generate a pulse corresponding to the change point of .
Since this pulse train k is synchronized with the phase quantized data train l, data input can be handled by making l the input data of the RAM and k the drive clock of the write address counter of the RAM. can be given a write address. Also, RAM data input
and the write clock k is already the read clock g
Since the phase of the clock g is quantized, for example, by allocating the high level period of the clock g to the read period and the low level period of the clock g to the write period, the RAM operation can be performed without any trouble. At this time, if necessary, the read address and write address are switched depending on whether it is a read period or a write period and given to the RAM, or a write enable control signal is supplied to the RAM at an appropriate phase within the write period. The technology is already known.
Control of writing and reading of the RAM 29 will be described in detail with reference to the example shown in FIG.

Write address counter 210 is driven by the output k of pulse generator 28, the output of which is shown in FIG. 4n.
Since k is a pulse at each change point of h, the counter driven by k changes in the same way at the time when the data input l of the random access memory changes.
In other words, a corresponding write address is given for each data input. The changing points of data input waveform l and write address waveform n both coincide with the rising point of read clock g, and the phases of input clock a and input data d are synchronized with the phase of read clock g, and the random access memory It will be given to the 29th.

Read counter 211 of random access memory 29
is driven 1 by the read clock g, and its output is shown in FIG. 40. X in o is an integer. The random access memory 29 adopts the read address o in the high level section of the read clock g, and
In the low level section of , write address n is adopted. The effective addresses of random address memory 29 are shown in FIG. 4p. As described above, all the random address memories 29 operate in accordance with the phase of the read clock g. In this case, the write enable control may be applied for each write period as shown in FIG. 4m, or may be applied only once every time the write address is changed.

If a method is adopted in which a write enable pulse is given every write period, if the data does not change, the same data will be written to the same address more than once, but there is no problem. Normally, the write address counter needs to be synchronized with the frame phase of the input data string, but if a frame synchronization circuit is used for this purpose, the frame synchronization circuit 61 is connected to the output point of the selector 27 as shown in FIG. , thereby writing address counter 21
0 can be controlled. In FIG. 6, the same numbers as in FIG. 2 indicate the same contents as in FIG. 2. Furthermore, when the write frame phase and the read frame phase are close to each other, by giving a certain delay to the input signal, the phases of the two can be shifted, thereby avoiding the risk of overflow or underflow of the buffer memory.

An example of the circuit configuration in that case is shown in FIG. In FIG. 7, 71 is a digital delay circuit, 72 is a second selector that selects either the input or output of the delay circuit 71, and 7
3 compares the phases of the write address counter and the read address counter, and according to the result, sends a control signal to the second selector 72, and also sends a control signal to the write address counter as necessary to synchronize the frame. This is a phase comparator that has the function of preventing deviation.
In FIG. 7, the same numbers as in FIG. 2 or 6 indicate the same contents as those in FIG. 2 or 6, respectively. The above explanation describes the circuit operation when the read clock frequency F2 is higher than the write clock frequency f1, but when the two clock frequencies are equal, F2=
2f1 and read out every other time, the circuit of the present invention can be used. FIG. 8 shows an example of the circuit configuration in that case. In FIG. 8, 81 is a 2 frequency divider circuit. In FIG. 2 and FIG. 8, the same numbers indicate the same contents. In FIG. 8, the repetition frequency of the clock supplied to terminal 23 is twice the readout clock frequency. As explained above, by using the circuit according to the present invention, an elastic buffer memory having a large capacity can be constructed with a simple circuit configuration.

[Brief explanation of the drawing]

Fig. 1 is an example of the frame structure of an input/output signal to which the circuit of the present invention is applied, Fig. 2 is a block diagram showing the circuit structure of the present invention, and Fig. 3 is a concrete example of a part of the circuit structure of the present invention. FIGS. 4 and 5 are timing diagrams for explaining the operation of the circuit configuration shown in FIG. FIG. 3 is a block diagram showing an example of the application of the circuit. In the figure, 21 is an input terminal for a digital signal, 22 is an input terminal for an input clock signal, 23 is an input terminal for an output clock signal, 24 is a divide-by-2 counter, 25 is a timing circuit, 26 is a memory, 27 is a selector, 28 is a pulse generator, 29 is a random access memory circuit (RAM),
210 is a counter that specifies a RAM write address; 211 is a counter that specifies a RAM read address; 212 is an input terminal for a write enable control signal; 213
is the output terminal of the RAM.

Claims (1)

[Claims] 1 an input terminal for a digital signal, an input terminal for a first clock phase synchronized with the digital signal, an input terminal for a second clock having a repetition frequency higher than the repetition frequency of the first clock, and an input terminal for a second clock having a repetition frequency higher than the repetition frequency of the first clock; a 2-bit memory circuit which receives the digital signal as input and expands and outputs two series of input signals for each bit under the control of the output of the 2-bit frequency divider circuit; a retiming circuit that retimes the output of the divide-by-2 circuit using the second clock; and a retiming circuit that retimes the output of the divide-by-2 circuit using the second clock;
a selection circuit having a function of selecting one of the two outputs, a counter that increments each time the output of the retiming circuit changes, and a random access memory that uses the output of the counter as a write address and the output of the selection circuit as a data input. A buffer memory circuit having.