JPH0213500B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention is a method for detecting phase fluctuations from an input data string having phase fluctuations caused by transmission paths between stations in a time-division switching network or the like. The present invention relates to a phase fluctuation absorbing device that absorbs and converts data into a data string regulated by the clock phase within the station.

In a time-division switching network, the entire network is constructed so that the clock frequencies of each switching station are equal to each other by a mutual synchronization method or a subordinate synchronization method. However, as the transmission path between exchanges expands and contracts due to temperature fluctuations, etc., the transmission delay time between exchanges changes. Furthermore, depending on the transmission method, jitter due to pattern fluctuations in the data string, especially low frequency components, is accumulated, and when the signal enters the exchange, large phase fluctuations occur along with the delay time fluctuations. In order to absorb such phase fluctuations at each exchange, a phase fluctuation absorbing device is provided.

[Prior art]

FIG. 1 is a block diagram showing a conventional device, and FIG. 2 is a waveform diagram showing signal waveforms at various parts of the device shown in FIG.

In these figures, reference numeral 1 denotes a storage device, which is constructed using a random access memory whose address input terminal is common for writing and reading. 2 is a write address generation device, 3 is a bit phase comparison circuit, 4 is an address switching circuit, 6 is a read address generation circuit, 7
are various timing signal generation circuits.

In addition, 8 is an input signal string, 9 is an input clock, 1
0 is a write address signal, 11 is an output signal of the bit phase comparison circuit 3, 12-1 is an address switching signal, 13 is a write/read specification signal, 14 is a comparison signal, 15 is a read address signal, 16 is a write/read timing signal , 17 is a write/read address signal, 18 is an output signal string, and 19 is an output side clock. In addition, the address switching signal 12-1 is shown in FIG.
4, the write/read designation signal includes signals 12-1, _12-2 , _{12-4 ,} and the write _/ read timing signal 16. consists of a write timing signal shown at 16-1 and a read timing signal shown at 16-2 in FIG.

The memory device 1 is used as a 1-bit, 1-address memory device, and the output side clock 19 consists of a pulse train with a bit period T, as shown in FIG. 2, and reads 1 bit of data from the memory device 1 for each pulse. This becomes the output signal sequence 18. The input clock 9 is connected to the output clock 19, for example by a second clock.
As shown in the figure, the bit phase comparison circuit 3 determines the phase of the clock 9 with respect to the clock 19. That is, the various timing signal generation circuits 7 output the second signal as the comparison signal 14.
As shown in the figure, a signal of logic "1" is output during the first half of a bit period T (hereinafter, the period of bit period T is referred to as one time slot) and a logic "0" signal is output during the second half.
The bit phase comparator circuit 3 outputs a signal 11 which is logic "1" when the clock 9 is in the first half of the time slot T, and logic "0" when it is in the second half.

On the other hand, various timing signal generation circuits 7 are connected to clocks 19, 12-1, 12-2, 12-
Generates four types of signals 3 and 12-4, and generates signal 12-
1 controls the address switching circuit 4, and the signal 12-
1, 12-2, and 12-4 are input to the selection circuit 5 as a signal 13. The content value of the write address signal 10 output from the write address generator 2 increases by 1 for each bit of the clock 9, and as shown in FIG. i
+1)→. Similarly, the content value of the read address signal 15 output from the read address generator 6 increases by 1 for each bit of the clock 19, and as shown in FIG.
1)→(j+2)→.

The address switching circuit 4 outputs the signal 15 as the signal 17 when the signal 12-1 is logic "1",
When the signal 12-1 is logic "0", the signal 10 is output as the signal 17. The selection circuit 5 receives the signal 12-1
is output as a read timing signal 16-2,
When the signal 11 is logic "1", the signal 12-2 is outputted as the write timing signal 16-1, and when the signal 11 is logic "0", the signal 12-4 is outputted as the write timing signal 16-1.

In this way, the input signal string 8 is written into the storage device 1 bit by bit, and read out from the storage device 1 bit by bit in the order of the written addresses, and each bit of the output signal string 18 is written into the storage device 1 bit by bit in the order of the written addresses. will be maintained.

The phase or frequency difference between signals 9 and 19 is 1
Either the signal h ₄ of one slot and the signal h ₂ of the following slot together become the write timing signal 16-1 (the case shown in FIG. 2 is an example of this), or the signal h ₂ of one slot This is absorbed by the subsequent slot signal _h4 , which together becomes the write timing signal 16-1.

The conventional device operates as described above, so that within one slot T, which is a relatively short period of time, the
Generate signals as shown as h ₁ , h ₂ , h ₃ , h ₄ ,
These signals must be used to control the address switching circuit 4 and the selection circuit 5, which requires circuit components to operate at high speed, requires a special storage device, and has the drawbacks of increasing costs. Ta.

[Summary of the invention]

This invention was made in order to eliminate the drawbacks of the conventional ones as described above.In this invention, a signal transmitted in a serial bit format is divided into m bits, and one data of M bits (M≧m) is divided. By absorbing phase fluctuations using a memory device, we constructed a device that does not require high-speed operation of circuit components.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 3 is a block diagram showing one embodiment of the present invention, and FIG. 4 is a waveform diagram showing signal waveforms at various parts in FIG. In these figures, the same reference numerals as in FIG. 1 indicate the same or equivalent parts, 21 is a serial-to-parallel conversion circuit, 22 is a FIFO (first-in-first-out) memory, 23 is a storage device, and 24 is a parallel-to-serial conversion circuit. Circuits 25 and 26 are ring counters, 27
is a write phase control circuit.

Further, 28 is one m-bit parallel data output from the serial/parallel conversion circuit 21, and 29 is one M-bit parallel data (M≧
m), 30 is one M-bit parallel data read from the storage device 23, 31 is an output signal of a suitable phase of the m-stage ring counter 25, 32 is a write address signal, 33 is a read address signal, 34
3 is an output signal of the address switching circuit 4, 35 is an output signal of a suitable phase of the m-stage ring counter 26, 36 is an output signal of the write phase control circuit 27, 3
7 is the output signal of the ring counter 26.

The input signal string 8 is inputted to the serial/parallel conversion circuit 21 in the form of bit series, and m-bit parallel 1 data 2
8 and is written to the FIFO memory 22. below,
For convenience of explanation, an example where m=4 will be explained. The ring counter 25 is an m-stage ring counter, and the fourth
The signal shown in FIG. 31 is generated to control writing to the FIFO memory 22. That is, FIFO memory 2
As shown in FIG. 4, the write data signal to 2 changes as D(i)→D(i+1)→D(i+2)→.

On the other hand, the ring counter 26 inputting the signal 19
generates a signal 37, and the read address generation circuit 6
The content numerical value of the read address 33, which is the output of
1)→(j+2)→, and therefore, one M-bit parallel data 30 read from the storage device 23 becomes D(j-1)→ as shown in FIG.
It changes as D(j) → D(j+1) → D(j+2) and is input to the parallel-to-serial conversion circuit 24, of which only m bits are read out by the signal 19 and output as the output side signal string 18. Output. M=m
Alternatively, one extra bit may be used for parity check by setting M=m+1, but the output side signal train 18 does not include the extra bit added within this device.

As shown in FIG. 4, signal 35 is advanced by a bit period T than signal 37. A signal 38 in FIG. 4 is a signal obtained by inverting the logical sum of signals 35 and 37, and is generated within the write phase control circuit 27.
is used to generate signal 36 from. In this specification, signals 31, 37, 35, and 36 are referred to as first, second, third, and fourth control signals, respectively, and signal 38 is referred to as a gate signal.

FIG. 5 is a waveform diagram illustrating the operation of the write phase control circuit 27 in FIG. 3, in which signals 37 and 38 are the same as signals 37 and 38 in FIG.
-1,36-1;31-2,36-2;31-
3 and 36-3 show three examples of the relative phases of signals 31 and 38 in FIG. 4 and the corresponding signal 36.

Signal 3 as shown in Figure 5 31-1, 36-1
1 is included in the logical "1" section of the signal 38 (section A in FIG. 5), the signal 31 is directly used as the signal 36, and the rising edge of the signal 31 falls within the section as shown in 31-2 and 36-2. A, and when the falling edge is within section B, the rising edge is made the rising edge of the signal 31, and the falling edge is made to match the rising edge of the signal 37 to create a signal 36, as shown in 31-3 and 36-3. If there is a rising edge of the signal 31 in section B, the rising edge is made to coincide with the rising edge of the signal 38 to generate a signal 36 having a width of the bit period T, which is used as the write control signal 36.

FIG. 4 shows the case where clock 9 is slower than clock 19. When the signal 36 is input, the write address generation circuit 2 generates a write address signal from i→(i+1)→(i+2)→(i+) as shown in FIG.
3), and FIFO memory 2 is changed by signal 36.
The signal 29 read from 2 is D(i)→D(i+1)→
Storage device 23 like D(i+2) and D(i-3)
write to.

Incidentally, the FIFO memory 22 is a buffer memory for preventing a part of the input signal string 8 from being dropped when the signal 31 is delayed by the write phase control circuit 27.

FIG. 6 is a block diagram showing another embodiment of the present invention, in which the same reference numerals as in FIG. 3 indicate the same or equivalent parts, M>m in the design of the circuit in FIG. 3, and 40 is inserted. Additional information bits 41 are extracted additional information bits. Examples of the additional information bits include bits for error detection or correction, or frame pulses accompanying the input signal sequence 8.

〔Effect of the invention〕

As described above, according to the present invention, by performing M-bit parallel writing/reading to a storage device, it is possible to use an inexpensive random access memory that does not require high-speed operation, and it is possible to use an inexpensive random access memory that does not require high-speed operation. In some cases, it is possible to provide a large-capacity and economical phase fluctuation absorber.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a conventional device, Fig. 2 is a waveform diagram showing signal waveforms of each part of the device in Fig. 1,
FIG. 3 is a block diagram showing an embodiment of this invention.
Figure 4 is a waveform diagram showing the signal waveforms of each part in Figure 3;
FIG. 5 is a waveform diagram explaining the operation of the write phase control circuit of FIG. 3, and FIG. 6 is a block diagram showing another embodiment of the present invention. 2...Write address generation circuit, 4...Address switching circuit, 6...Read address generation circuit, 8
...Input signal string, 9...Input clock, 18...
Output signal string, 19... Output side clock, 21...
Serial-parallel conversion circuit, 22... FIFO memory, 23
...Storage device, 24...Parallel-serial conversion circuit, 27
...Write phase control circuit, 31, 37, 35, 3
6...first, second, third, and fourth control signals, 38
...Gate signal. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] 1. In a phase fluctuation absorbing device that converts an input signal train having a phase fluctuation with respect to an output side clock to an output side signal train regulated by the output side clock via a storage device, M and m is an integer that satisfies the condition of Mm4, and a serial-to-parallel conversion circuit divides an input signal string input in the form of bit series into m-bit signals and converts them into parallel m-bit signals. means for generating a first control signal having a pulse repetition period m times the bit period and a pulse width equal to the bit period; A means for writing into M bit 1 data of a FIFO memory which is a memory device read out sequentially, inputting an output side clock and having a pulse repetition period m times the bit period T of the output side clock. the second with a pulse width equal to
means for generating a control signal; generating a third control signal having the same waveform as the second control signal and leading in phase from the second control signal by the bit period T of the output clock; means for generating a gate signal by inverting the signal logic of the logical sum of the third control signal and the second control signal, wherein both the rising point and the falling point of the first control signal are within the gate signal; , the first control signal is used as the fourth control signal, and the rising point of the first control signal is within the gate signal and the falling point of the first control signal is outside the gate signal. when the rising point of the first control signal is the rising point of the fourth control signal, and the subsequent falling point of the third control signal is the falling point of the fourth control signal, When both the rising point and the falling point of the first control signal are outside the gate signal, the rising point of the gate signal following the falling point of the first control signal is the rising point of the fourth control signal. a write phase control circuit that outputs a fourth control signal with the pulse width of the fourth control signal being T;
Means for writing M-bit data in the FIFO memory as M-bit data in a storage device in address order by a control signal, and reading M-bit data in the storage device in address order by a second control signal; A parallel converter that inputs m bits corresponding to the m bits input from the serial/parallel converter out of the M bit data read out from the serial parallel converter, reads this out using the output side clock, and outputs it as an output signal string in the form of a bit series. A phase fluctuation absorbing device characterized by comprising a serial conversion circuit.