JP2513132B2 - Signal speed converter - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal converter for converting a plurality of asynchronous input data signals into a plurality of output data signals having a signal speed sufficiently higher than those signals in a digital signal transmission system. Here, the clock synchronized with each bit of the input data signal is, for example, several k.
A clock having a frequency of Hz and synchronized with each bit of the output data signal has a frequency of several MHz, for example.

[0002]

2. Description of the Related Art A signal rate conversion device in a digital signal transmission system uses a FIFO (First In First Ox) to convert a transmission signal into different signal rates.
memory) and RAM (Random Access)
Memory) is used as a speed conversion circuit (JP-A-2-128535, JP-A-57-241).
No. 41).

As shown in FIG. 2, such a signal speed conversion apparatus has a plurality of asynchronous input data signals (low speed).
a _1, a _2, ..., respectively a _n a timing synchronized with the clock (low speed) b _1, b _2, ..., based on b _n, a plurality of timing signal generation circuit 60-1 and 60-2, ..., 60 −
a plurality of speed conversion circuits 30-1, 30-2,
.., 30-n write timing signals i ₁ , i ₂ ,
, I _n and write the data signals a _{1 to} a _n into the speed conversion circuits 30-1 to 30-n, respectively, and the timing signal generation circuit 5 from the clock (high speed) c ₃ after speed conversion.
Output data signal by the generated read timing signal j from the speed converting circuit 30-1 to 30-n in 0B _{(fast) f 1, f 2, ...} , reads the f _n.

[0004]

Since the conventional signal speed conversion apparatus generates the write timing signal by the clock synchronized with the input data signal as described above, the write timing signal is input when a plurality of asynchronous signals are input. Need to be generated individually. for that reason,
Must have individually for the timing signal generating circuit 60-1 to 60-n and the speed converting circuit 30-1 to 30-n each data signal a ₁ ~a _n.

Further, since the phase of input data and the phase of output data are not fixed in a speed conversion circuit such as a FIFO, it is necessary to manage the phases on the writing side and the reading side so as not to cause a data reading error. For these reasons, large scale circuits are required to convert multiple asynchronous input data signals.

Therefore, an object of the present invention is to provide a signal conversion device capable of reducing the circuit scale.

[0007]

According to the present invention, asynchronous first to nth (n is 2) having the same input signal rate.
In the signal speed conversion device for converting the respective input data signals of the above integers into the first to nth output data signals having the same output signal speed higher than these signals,
A sampling circuit for commonly sampling the first to nth input data signals with a clock having a frequency higher than the clock frequency of these signals, and outputting the first to nth sampled signals respectively; First
Through the first clock from the clock of the nth input data signal
To a phase determination circuit that determines periodic data change points of the n-th input data signal and outputs change point timing information indicating these data change points, and the data change indicated by the change point timing information Points other than points,
A timing signal generation circuit for generating a phase alignment timing signal having the same period as the period of the first to nth input data signals, and the first to nth sampled signals based on the phase alignment timing signal. Phase aligning circuit for aligning the phases of the signals, and outputting the first to nth phase aligned signals, respectively, and the first to nth
And a speed conversion circuit that outputs the first to nth output data signals by speed-converting the signals whose phases are aligned with a common speed conversion timing signal. can get.

Further, according to the present invention, the sampling circuit performs common sampling with a clock having a frequency equal to the frequency of the clock of the first to n-th output data signals, and the first to n-th samplings. A signal speed conversion device is obtained which is characterized in that it outputs the respective generated signals.

Further, according to the present invention, the timing signal generating circuit is supplied with a clock having a frequency equal to the frequency of the clock of the first to nth output data signals,
A signal speed conversion apparatus is also provided, which is characterized in that the speed conversion timing signal is also generated and sent to the speed conversion circuit.

[0010]

Next, an embodiment of the present invention will be described with reference to the drawings.

Referring to FIG. 1, a signal rate converter according to an embodiment of the present invention outputs asynchronous first to nth input data signals a _{1 to} a _n having the same input signal rate. respectively into a first or output data signal f ₁ ~f _n of the n with a higher same output signal speed. The present signal speed conversion device commonly samples the _first to nth input data signals a _{1 to} a _n with a clock c ₁ having a frequency higher than the clock frequency of these signals,
The sampling circuit 10 outputs the _first to nth sampled signals d _{1 to} d _n , respectively.

[0012] phase determination circuit 40, a cyclic data change point (bit of the input data signal a ₁ ~a _n of the input data signal a ₁ ~a _n first through n from the clock of the first to n (Point between the bit) and the change point timing information g indicating these data change points are output. The timing signal generation circuit 50A indicates points other than the data change points indicated by the change point timing information g. Generating a phase alignment timing signal h having the same period as that of the input data signal a ₁ ~a _n of first through n.

FIG. 3 shows the first to nth input data signals a ₁
~ A _n and the phase alignment timing signal h are shown. Timing signal h ₁ phase alignment is consistent with the data change point of the input data signal a _n, the timing signal h ₂ phase alignment is not also match the data change point of any input data signal a ₁ ~a _n. Therefore, the timing signal generation circuit 50A outputs the phase alignment timing signal h ₂ as the phase alignment timing signal h.

[0014] In FIG. 1, the phase alignment circuit 20, based on the phase alignment timing signal h, aligns the phase of the sampled signal d ₁ to d _n of first through n, first through phase of the n and it outputs the signal e ₁ to e _n which is aligned with. Speed conversion circuit 30 is aligned with the first through the n-th phase by speed conversion signals e ₁ to e _n at a common speed conversion timing signal (write timing signal i and a read timing signal j), first to It outputs n output data signals f _{1 to} f _n .

The sampling circuit 10 performs common sampling with a clock c ₁ having a frequency equal to the frequencies of the clocks of the _first to _nth output data signals f _{1 to} f _n , and is sampled from the 1st to the nth. The signals d _{1 to} d _n are output respectively. Further, the timing signal generation circuit 50A is
A clock c of the _{first to nth} output data signals f _{1 to} f _n
Is supplied with a clock c ₂ having a frequency equal to ₁
The speed conversion timing signals i and j described above are also generated and sent to the speed conversion circuit 30.

Next, the operation of the signal speed converter of FIG. 1 will be described.

Input data signals a _{1 to} a _n asynchronous with each other
Are sampled by the sampling circuit 10 at the clock c ₁ after the speed conversion of these data is sufficiently high. Data signals d _{1 to} d after this sampling
A timing signal generation circuit 5 using the same clock c ₂ as that sampled by inputting _n to the phase alignment circuit 20.
All the phases of the plurality of data signals are aligned by extracting with the sampling pulse (which corresponds to the phase alignment timing signal) h having the same cycle as the data signal, which is created by 0A. At this time, if the sampling pulse h hits the change point of the data signal as indicated by h ₁ in FIG. 3, a data reading error occurs, so that the timing clock d ₁ having the same phase as the input data.
To d _n are input to the phase determination circuit 40, and each data signal a ₁
By sending a change point timing information g of ~a _n to the timing signal generation circuit 50A, to generate a sampling pulse to a position avoiding a signal change point as h ₂ in Fig. The phase-aligned data signals e _{1 to} e _n are input to the speed conversion circuit 30 and speed-converted by the write timing signal i and the read timing signal j from the timing signal generation circuit 50A, and high-speed data signals f _{1 to} f _n. Becomes

As described above, in this embodiment, the input data signal is sampled by the clock after the speed conversion on the assumption that the signal speed after the conversion is sufficiently higher than the signal speed of the input data, and the data is sampled before and after the conversion circuit. Eliminates the need for phase management by operating with the same clock, and aligns the phases of multiple signals based on the phase alignment timing signal with the same period as the input data, and uses the same speed conversion circuit to reduce the circuit scale. We are trying to reduce it.

[0019]

As described in detail above, when the signal speed converter of the present invention is used, the phases of a plurality of asynchronous data signals are input to the speed converter circuit in the same phase, so that the same timing signal generation circuit and speed controller are used. A conversion circuit can be used.

Further, since writing and reading to and from the speed conversion circuit are controlled by the same timing generation circuit, there is no possibility of a reading error and the circuit scale can be greatly reduced by eliminating the need for a phase management circuit.

[Brief description of drawings]

FIG. 1 is a block diagram of a signal speed conversion circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional signal speed conversion circuit.

FIG. 3 is a diagram for explaining the operation of FIG.

[Explanation of symbols]

 10 Sampling circuit 20 Phase alignment circuit 30 Speed conversion circuit 40 Phase determination circuit 50A Timing signal generation circuit 30-1 to 30-n Speed conversion circuit 50B Timing signal generation circuit 60-1 to 60-N Timing signal generation circuit

Claims (3)

(57) [Claims] 1. Asynchronous first to n-th (n is an integer greater than or equal to 2) input data signals having the same input signal rate, and first to first signals having the same output signal rate higher than these signals. In a signal speed conversion device for converting each of the n to n output data signals, the first to nth input data signals are commonly sampled by a clock having a frequency higher than the clock frequency of these signals, and the first to nth a sampling circuit for outputting n sampled signals respectively, and determining a periodic data change point of the first to nth input data signals from the clocks of the first to nth input data signals, A phase determination circuit that outputs change point timing information indicating these data change points, and points other than the data change points indicated by the change point timing information are shown. A timing signal generating circuit that generates a phase alignment timing signal having the same period as the period of the first to nth input data signals; and the first to nth reference signals based on the phase alignment timing signal. A phase alignment circuit that aligns the phases of the sampled signals and outputs signals that are aligned in the first to nth phases, respectively, and a common speed conversion timing for the signals that are aligned in the first to nth phases. A speed conversion circuit that performs speed conversion with a signal and outputs the first to nth output data signals,
A signal speed conversion device having. 2. The sampling circuit commonly samples with a clock having a frequency equal to the frequency of the clock of the first to n-th output data signals, and respectively samples the first to n-th sampled signals. The signal speed conversion device according to claim 1, wherein the signal speed conversion device outputs the signal. 3. The timing signal generating circuit is supplied with a clock having a frequency equal to the frequency of the clocks of the first to nth output data signals, and also generates the speed conversion timing signal. The signal speed conversion device according to claim 2, wherein the signal speed conversion device transmits the signal to the signal speed conversion device.