JPH0955723A - Clock replacing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock replacing circuit which does not malfunctions frequently owing to noise and is suitable for verification by a CAD tool. SOLUTION: A register 15 has (n) storage areas wherein data of one bit can be stored. A write counter 16 divides the frequency of a write clock signal WC to generate write pulse signals WP1-WPn which have high-level periods and low-level periods of >=2-clock width. A read counter 17 divides the frequency of a read clock signal RC to generate read pulse signals RP1-RPn. Latch circuits 181 and 182 latch the write pulse signals WPi in order according to the clock signal RC. A latch circuit 183, AND circuits 184 and 186, and an OR circuit 185 compare the phase of the latch output of the latch circuit 182 with those of corresponding read pulse signals RPi+2 to generate the self-reset signal P3 of the read counter 17.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock transfer circuit used as an elastic store circuit in a communication device, for example.

[0002]

2. Description of the Related Art Generally, a communication device is provided with an elastic store circuit for the purpose of suppressing fluctuation of received data.

This elastic store circuit writes data in the memory in accordance with the frequency-divided output of the write clock signal extracted from the transmission path, and reads this write data in accordance with the frequency-divided output of the read clock signal generated inside the communication device. As a result, fluctuations of received data are suppressed.

By the way, in this elastic store circuit, writing and reading of data are performed in parallel. Therefore, when the data writing phase and the data reading phase are close to each other, data writing may be performed during data reading, and a read error may occur.

In order to deal with this problem, the elastic store circuit is usually provided with a self-reset circuit.

This self-resetting circuit compares the write phase and the read phase of data, and when the phase difference between the two becomes less than a predetermined value, the frequency dividing counter on the read side (or the write side) is reset to write data. The phase and the read phase are prevented from approaching each other.

In this case, the conventional self-reset circuit first generates a self-reset signal by taking the logical product of the divided output of the write clock signal (or the read clock signal) and the pulse signal indicating the reset area, Next, the self-reset signal is latched by the read clock signal (or the write clock signal) so that it can be transferred to the read clock signal (or the write clock signal).

However, in such a configuration, if the difference between the write phase and the read phase becomes smaller than one clock width, it may not be possible to latch the self-reset signal. This is because in such a case, the latch timing of the self-reset signal is only once, and this timing overlaps the rear edge of the self-reset signal.

To solve this problem, it is conceivable to extend the width (pulse width) of the active level of the self-reset signal backward.

However, in the configuration in which the self-reset signal is generated by taking the logical product of the divided output of the write clock signal (or the read clock signal) and the reset area display signal, the width of the active level of the self-reset signal is set backward. Cannot be extended to. This is because in such a configuration, the position of the rear edge of the self-reset signal is restricted by the rear edge of the reset area display signal.

[0011] Therefore, conventionally, RS is used as a self-reset signal.
By setting the flip-flop circuit and latching the set output according to the read clock signal (or write clock signal), the self-reset signal is transferred to the read clock signal (or write clock signal).

[0012]

However, in the configuration in which the RS flip-flop circuit is used to transfer the self-reset signal to the read clock signal (or write clock signal), the RS flip-flop circuit is easily affected by noise. Therefore, there is a problem that malfunction due to noise is likely to occur.

Further, with such a configuration, there is a problem that it cannot be verified by a computer-aided design tool (hereinafter referred to as "CAD tool") used in verification of a large-scale circuit design. This is because the RS flip-flop circuit is an asynchronous register, while the CAD
This is because the tool assumes synchronous design.

[0014]

In order to solve the above-mentioned problems, the invention according to claim 1 provides a width between a high level period and a low level period of a plurality of write pulse signals obtained by dividing a write clock signal. Is set to a width of 2 clocks or more, and the write pulse signals selected from the plurality of write pulse signals as signals for phase comparison are sequentially latched according to the read clock signal by at least two latch circuits connected in series. The phase of the final latch output is compared with the phase of the read pulse signal corresponding to the final latch output, and the read pulse generating means is reset based on the comparison result.

Similarly, in the invention according to claim 5, the widths of the high level period and the low level period of the plurality of read pulse signals obtained by dividing the read clock signal are both set to two clock widths or more, A read pulse signal selected as a signal for phase comparison from the plurality of read pulse signals is sequentially latched according to the write clock signal by at least two latch circuits connected in series, and the final latch output and the final latch output are obtained. The phase is compared with that of the corresponding write pulse signal, and the write pulse generating means is reset based on the comparison result.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

[First Embodiment] First, a first embodiment of the present invention will be described.

In the following description, the case where the present invention is applied to an elastic store circuit will be described as a representative.

[Structure] FIG. 1 is a circuit diagram showing the structure of a first embodiment of the present invention.

Incidentally, FIG. 1 shows the case where the depth of the elastic store circuit is n as a representative. here,
Although n will be described in detail later, n is an integer of 4 or more.

First, the function of each part of the elastic store circuit shown in FIG. 1 will be described.

The illustrated elastic store circuit has a data input terminal 11, a data output terminal 12, a write clock input terminal 13, a read clock input terminal 14, and
It has a register 15, a write counter 16, a read counter 17, and a self-resetting circuit 18.

To the data input terminal 11, data D in the bit serial format sent via a transmission line (not shown).
Is supplied.

The data output terminal 12 is supplied with the data D in the bit serial format read from the register 15.

The write clock input terminal 13 is supplied with the write clock signal WC extracted from the transmission line.
The write clock signal WC is synchronized with the data D supplied to the data input terminal 11.

A read clock signal RC generated inside the communication device is supplied to the read clock input terminal 14. The read clock signal RC is asynchronous with the write clock signal WC and has the same frequency.

The register 15 has n storage areas capable of storing 1-bit data and is used for storing the data D.

The write counter 16 has a function of generating n write pulse signals WP1 to WPn by dividing the write clock signal WC by n. The phases of the n write pulse signals WP1 to WPn are shifted from each other by one clock width of the write clock signal WC. Also,
The widths of the high level period and the low level period are both set to be two clock widths or more of the write clock signal WC. As a result, in this embodiment, n is set to an integer of 4 or more.

The read counter 17 has a function of dividing the read clock signal RC to generate n read pulse signals RP1 to RPn. The phases of the n read pulse signals RP1 to RPn are shifted from each other by one clock width of the read clock signal RC. The width of the active level (pulse width) is set to, for example, one clock width of the read clock signal RC.

The self-resetting circuit 18 sets the phase of the write pulse signal WPi (i is an arbitrary integer of 1≤i≤n) selected from the n write pulse signals WP1 to WPn as a signal for phase comparison, and Corresponding read pulse signal R
It has a function of comparing the phases of Pi and resetting the read counter 17 when the phase difference between them becomes, for example, 2 clock widths or less.

The self-reset circuit 18 has latch circuits 181, 182, 183, an AND circuit 184, an OR circuit 185, and an AND circuit 186.

The latch circuits 181 and 182 have write pulse signals WPi (i is 1≤i≤n) selected from the n write pulse signals WP1 to WPn as signals for phase comparison.
By latching the write pulse signal WPi from the write clock signal WC to the read clock signal RC.

In this case, the latch circuits 181, 182 are
Connected in series to form a two-stage shift register,
The write pulse signal WPi is sequentially latched according to the read clock signal RC.

The latch circuit 183 and the AND circuit 184 are
The write pulse signal WP latched by the latch circuit 182
It has a function of generating a pulse signal indicating the phase of the rising edge of i, in other words, a pulse signal indicating the writing phase (hereinafter referred to as “writing phase display signal”) P1.

The OR circuit 185 outputs the read pulse signal RP.
It has a function of generating a reset area display signal P2 indicating the reset area of the read counter 17 by taking the logical sum of i + 2 and RPi + 3.

The reset area display signal P2 is used as the read pulse signal RP corresponding to the write pulse signal WPi.
The write pulse signal WPi is generated by the logical sum of the read pulse signals RPi + 2 and RPi + 3 instead of the logical sum of i and the read pulse signal RPi + 1 subsequent thereto.
Is shifted by 2 clocks of the read clock signal RC by the latch circuits 181 and 182.

The AND circuit 186 has a function of generating the reset signal P3 of the read counter 17 by taking the logical product of the write phase display signal P1 and the reset area display signal P2.

The above is the function of each part of the elastic store circuit shown in FIG.

Next, the connection configuration of each part of the elastic store circuit will be described.

The data input terminal 11 is connected to the data input terminal I of the register 15. The data output terminal O of the register 15 is connected to the data output terminal 12.

The write clock input terminal 13 is connected to the clock input terminal WCK of the write counter 16. The read clock input terminal 14 includes a clock input terminal RCK of the register 15, a clock input terminal RCK of the read counter 17, and latch circuits 181, 182, 18
3 clock input terminals.

The n write pulse output terminals Q1 to Qn of the write counter 16 are connected to the n write pulse input terminals Q1 to Qn of the register 15, respectively. The n read pulse output terminals Q1 to Q1 of the read counter 17
Qn is connected to n read pulse input terminals Q1 to Qn of the register 15, respectively.

The write pulse output terminal Qi of the write counter 16 is connected to the input terminal of the latch circuit 181. The non-inverting output terminal of the latch circuit 181 is connected to the input terminal of the latch circuit 182.

The non-inverting output terminal of the latch circuit 182 is connected to the input terminal of the latch circuit 183 and the 2-input AND circuit 184.
Connected to one of the input terminals. Latch circuit 183
The inverting output terminal of is connected to the other input terminal of the 2-input AND circuit 184.

The read pulse output terminals Qi + 2 and Qi + 3 of the read counter 17 are connected to the respective input terminals of the 2-input OR circuit 184. The output terminals of the AND circuit 184 and the OR circuit 185 are two-input AND circuit 186, respectively.
Are connected to each input terminal. The output terminal of the AND circuit 183 is connected to the reset terminal RST of the read counter 17.

The above is the connection configuration of each part of the elastic store circuit shown in FIG.

[Operation] The operation of the above configuration will be described.

First, the operation of writing the data D in the register 15 will be described.

The data D sent through a transmission line (not shown) is supplied to the data input terminal 11. The write clock input terminal 13 is supplied with the write clock signal WC extracted from a transmission line (not shown).

Data D supplied to the data input terminal 11
Is supplied to the data input terminal I of the register 15. The write clock signal WC supplied to the write clock input terminal 13 is the clock input terminal W of the write counter 16.
Supplied to CK.

The write clock signal WC supplied to the write counter 16 is divided by n. As a result, n write pulse signals WP1 to WPn are generated. The write pulse signals WP1 to WPn are respectively stored in the register 1
5 corresponding write pulse input terminals Q1 to Qn.

FIG. 2 shows the write clock signal WC and n write pulse signals WP1 to WPn.

In the figure, for example, positive polarity write pulse signals WP1 to WPn are shown. This write pulse signal WP1
The phases of ˜WPn are the same as those of the write clock signal WC.
It is offset by the clock width. Further, in the case of the illustrated example, the width of the high level period of the write pulse signals WP1 to WPn (in the present example, the pulse width) is the write clock signal WC.
The width of the low level period is
(N-2) Clock width is set.

The data D supplied to the register 15 is sequentially written into the n storage areas of the register 15 at the rising edge timings of the write pulse signals WP1 to WPn for each bit.

The above is the write operation of the data D.

Next, the read operation of the data D will be described.

The read clock signal RC generated inside the communication device is supplied to the read clock input terminal 14. The read clock signal RC is a signal that is asynchronous with the write clock signal WC and has the same frequency.

The read clock signal RC is supplied to the clock input terminal RCK of the read counter 17. Read clock signal RC supplied to the read counter 17
Is divided by n. As a result, n read pulse signals RP1 to RPn are generated. The read pulse signals RP1 to RPn are supplied to the corresponding read pulse input terminals Q1 to Qn of the register 15, respectively.

FIG. 3 shows the read clock signal RC and the n read pulse signals RP1 to RPn.

In the figure, for example, the positive read pulse signals RP1 to RPn are shown. As illustrated, the read pulse signals RP1 to RPn are out of phase with each other by one clock cycle of the read clock signal RC. Further, in the case of the illustrated example, the width of the high level period of each read pulse signal RP1 to RPn (in the present example, the pulse width) is set to one clock width of the read clock signal WC, and the width of the low level period is , (N-1) clock cycles.

The data D written in the register 15 is
The corresponding read pulse signals RP1 to R for each bit
When Pn becomes active, it is read sequentially. The read data is latched for each bit according to the read clock signal RCK. As a result, the data D is read to the data output terminal 13 in the bit serial format.

From the above, a certain write pulse signal WPj
The bit data written in the jth storage area of the register 15 at the timing of the rising edge of (j is an arbitrary value of 1 ≦ j ≦ n) is read when the read pulse signal RPj becomes active. Be done.

The above is the read operation of the data D.

Next, the self-resetting operation of the read counter 17 will be described. First, the outline of this self-reset operation will be described.

The self-reset circuit 18 compares the phases of the write pulse signal WPi and the read pulse signal RPi, and generates the reset signal P3 when the phase difference between the two is less than two clock cycles of the read clock signal RC. As a result, the read counter 17 is reset. as a result,
The writing phase and the reading phase are prevented from approaching each other, and a reading error is prevented from occurring.

However, in this embodiment, since the write pulse signal WPi is shifted by 2 clocks, in reality, between the shifted write pulse signal WPi and the read pulse signal RPi + 2 corresponding thereto, Phase comparison is made.

The above is the outline of the self-reset operation.

Next, the self-reset operation will be described in detail.

The write pulse signal WPi output from the write counter 16 is supplied to the latch circuit 181, and is latched according to the read clock signal RC. As a result, the write pulse signal WPi becomes the write clock signal W.
The read clock signal RC is transferred from C.

In this case, since the width of the high level period of the write pulse signal WPi is set to 2 clock cycles and the width of the low level period is set to (n-2) clock cycles, the high level period and the low level period are Both are securely latched.

That is, as the width of the high level period and the low level period of the write pulse signal WPi, it is considered that either one is set to one clock width or less.

However, in this case, since the phase relationship between the write clock signal WC and the read clock signal RC is unknown, it may not be possible to latch the high level period or the low level period of the write pulse signal WPi. Therefore, in this case, it is necessary to set the RS flip-flop circuit by the write pulse signal WPi and latch the set output according to the read clock signal RC.

However, this causes the same problem as in the conventional configuration.

Therefore, in this embodiment, paying attention to the fact that the phase of the rear edge (falling edge in the example of FIG. 2) of the write pulse signal WPi can be freely set, and the write pulse signal WPi is set. The width of the high level period is 2
Set the clock width to the width of the low level period (n-2)
It is set to be wider than the clock width.

With such a configuration, even if the phase relationship between the write clock signal WC and the read clock signal RC is unknown, the high level period and the low level period can be reliably latched without using the RS flip-flop circuit. can do.

The latch output P4 of the latch circuit 181 is latched by the latch circuit 182 according to the read clock signal RC. The latch output P5 of the latch circuit 182 is latched by the latch circuit 183 according to the read clock signal RC.

The latch output P5 of the latch circuit 182 and the inverted output P6 of the latch circuit 183 are logically ANDed by the AND circuit 184. As a result, a signal indicating the phase of the rising edge of the write pulse signal WPi latched by the latch circuit 182, that is, the write phase display signal P1 is obtained.

The latch output P5 of the latch circuit 182 is used instead of the latch output P4 of the latch circuit 181 to generate the write phase display signal P1 because the latch output P4 of the latch circuit 181 becomes metastable. Because there is a possibility.

That is, when the phase relationship between the write clock signal WC and the read clock signal RC is unknown, the latch output P4 of the latch circuit 181 may become metastable.

However, the latch output P of the latch circuit 181 is
When 4 becomes metastable, the write phase display signal P1 cannot be generated based on this latch output P4.

Therefore, in this embodiment, the latch output P4 of the latch circuit 181 is further latched by the latch circuit 182.

According to such a configuration, the latch circuit 18
Even if the output P4 becomes metastable at the time of latching 1, the latch output P4 does not become metastable because the latch output P4 transits to a stable state within one clock cycle. This allows
In this case, the write phase display signal P1 can be reliably generated.

Write clock signal WC, write pulse signal WPi, read clock signal RC, and latch outputs P4, P5, P6 of latch circuits 181, 182, 183.
And the write phase display signal P1 is shown in FIG.

The read pulse signals RPi + 2 and RPi + 3 output from the read counter 17 are supplied to the OR circuit 185.
Is ORed by. As a result, the reset area display signal P2 having a pulse width of 2 clock widths from the timing of the rising edge of the read pulse signal RPi + 2.
Is generated.

The write phase display signal P1 and the reset area display signal P2 are logically ANDed by the AND circuit 186. As a result, the self-reset signal P3 is generated.
The phase of the rising edge of this self-reset signal P3 is
The phase of the falling edge coincides with the phase of the rising edge of the write phase display signal P1, and the phase of the falling edge is the reset area display signal P.
It matches the phase of the falling edge of 2.

The read counter 17 is reset at the timing of the rising edge of the reset signal P3.

FIG. 4 shows read pulse signals RPi and RPi.
+1, RPi + 2, RPi + 3 and reset area signal P
2 and the self-reset signal P3.

[Effect] According to this embodiment described in detail above, the following effects can be obtained.

(1) First, according to this embodiment, the widths of the high-level period and the low-level period of the write pulse signal WPi for phase comparison are set to 2 clock widths or more, and the write pulse signal WPi is set to the read clock. Since the self-reset signal P3 is generated by phase comparison after being latched by the signal RC, the clocks can be replaced without using the RS flip-flop circuit. As a result, there are few malfunctions due to noise, and
An elastic store circuit suitable for verification by a CAD tool can be provided.

(2) According to this embodiment, when the write pulse signal WPi is latched according to the read clock signal RC, the two latch circuits 181 and 182 are used to sequentially latch the latched signal. Even if the latch output P4 of 181 becomes metastable,
The write pulse signal WPi can be surely latched.

[Second Embodiment] Next, a second embodiment of the present invention will be described.

[Structure] In the above embodiment, the case where the self-reset circuit is formed without using the RS flip-flop circuit has been described.

On the other hand, in this embodiment, not only the self-reset circuit but also the external reset circuit is constructed without using the RS flip-flop circuit.

Here, the external reset circuit is a circuit that resets the write counter and the read counter by an external reset signal given from the outside when the power is turned on.

FIG. 5 is a circuit diagram showing the configuration of the second embodiment.

Note that, in FIG. 5, parts that perform substantially the same functions as in FIG. 1 are assigned the same reference numerals and detailed explanations thereof will be omitted.

The illustrated elastic store circuit is shown in FIG.
This elastic store circuit has a configuration in which an external reset input terminal 19, an external reset circuit 20, and an OR circuit 21 are added.

First, these functions will be described.

An external reset signal P7 for resetting the write counter 16 and the read counter 17 is supplied to the external reset terminal 19 when the power is turned on.

The external reset signal P7 is usually asynchronous with the write clock signal WC and the read clock signal RC. In this, the elastic store circuit serves as an interface for two synchronous systems.

The width (pulse width) of the active level of the external reset signal P7 is the same as the write clock signal W.
The width is 2 clock widths or more of C. This is to ensure that the external reset signal P7 can be latched by the write clock signal WC.

The external reset circuit 20 receives the external reset signal P7 supplied via the external reset input terminal 19, and the reset terminal RST of the write counter 16 and
It has a function of supplying one input terminal of the 2-input OR circuit 21.

The OR circuit 21 takes the logical sum of the self-reset signal P3 generated by the self-reset circuit 18 and the external reset signal P7 received by the external reset circuit 20 and supplies it to the reset terminal RST of the read counter 17. Have a function.

The read counter 17 has a reset terminal RS.
When a reset signal is supplied to T, it is configured to be reset to the same value regardless of whether it is the self-reset signal P3 or the external reset signal P7.

The external reset circuit 20 is the latch circuit 20.
It has 1,202,203,204.

The latch circuits 201 and 202 have a function of latching the external reset signal P7 in accordance with the write clock signal WC to transfer the external reset signal P7 from the external clock signal to the write clock signal WC.

In this case, the latch circuits 201 and 202 are
Connected in series to form a two-stage shift register,
The external reset signal P7 is sequentially latched according to the write clock signal WC.

The latch circuits 203 and 204 have a function of latching the latch output of the latch circuit 201 in accordance with the read clock signal WC to transfer the latch output from the write clock signal WC to the read clock signal RC.

In this case, the latch circuits 203 and 204 are
Connected in series to form a two-stage shift register,
The latch output of the latch circuit 201 is read as a clock signal R
According to C, it latches sequentially.

The above is the function of the part related to the external reset.

Next, the connection structure of the portion related to the external reset will be described.

The external reset input terminal 19 is connected to the input terminal of the latch circuit 201. This latch circuit 2
The non-inverting output terminal of 01 is connected to the input terminals of the latch circuits 202 and 203. The non-inverting output terminal of the latch circuit 202 is the reset terminal RST of the write counter 16.
It is connected to the.

The non-inverting output terminal of the latch circuit 203 is connected to the input terminal of the latch circuit 204. The non-inverting output terminal of the latch circuit 204 is connected to one input terminal of the 2-input OR circuit 21. This 2-input OR circuit 2
The output terminal of the AND circuit 186 is connected to the other input terminal of 1. The output terminal of the OR circuit 21 is connected to the reset terminal RST of the read counter 17.

The write clock input terminal 13 is connected to the clock input terminals of the latch circuits 201 and 202. The read clock input terminal 14 is connected to the clock input terminals of the latch circuits 203 and 204.

The above is the connection configuration of the part related to the external reset.

[Operation] The operation of the above configuration will be described.

In the following description, the external reset operation, which is a feature of this embodiment, will be mainly described.

First, the outline of the external reset operation will be described.

When the power is turned on, the reset signal P7 supplied to the external reset terminal 19 is supplied to the external reset circuit 20. The external reset signal P7 supplied to the external reset circuit 20 is transferred to the write clock signal WC and then supplied to the reset terminal RST of the write counter 16. As a result, the write counter 16 is reset to a predetermined value.

The external reset signal P7 supplied to the external reset receiving circuit 20 is further read as the read clock signal R.
After being transferred to C, it is supplied to the reset terminal RST of the read counter 17 via the OR circuit 21. As a result, the read counter 17 is reset to a predetermined value.

In this case, the reset value of the write counter 16 is set to a value far from the reset value of the read counter 17. This is to allow a margin between the writing phase and the reading phase of the data D.

The above is the outline of the external reset operation.

Next, the operation of the external reset circuit 20 will be described.

The external reset signal P7 supplied to the external reset terminal 19 is supplied to the latch circuit 201 and latched according to the write clock signal WC. As a result, the external reset signal P7 is transferred from the external clock signal to the write clock signal WC.

In this case, since the width of the active level period of the external reset signal P7, for example, the "1" level period is set to 2 clock widths or more, this active level period is surely latched.

That is, conventionally, the external reset signal P7 is used.
The width of the active level period is set to 1 clock width.

However, in this case, since the phase relationship between the external clock signal and the write clock signal WC is unknown, it may not be possible to latch the active level period of the write pulse signal WPi.

Therefore, conventionally, the RS flip-flop circuit is set by the external reset signal P7 and the set output is latched by the write clock signal WC.

However, such a configuration has problems that the external reset circuit 20 is also prone to malfunction due to noise and that it cannot be verified by a CAD tool.

On the other hand, in this embodiment, since the active level period of the external reset signal P7 is set to 2 clock width or more, the active level period is surely latched without using the RS flip-flop circuit. be able to. This makes it possible to configure an external reset circuit which is less likely to malfunction due to noise and suitable for verification by a CAD tool.

However, in such a configuration, the latch circuit 2
The 01 latch output may become metastable. This is the external clock signal and the write clock signal W.
This is because the phase relationship with C is unknown.

Therefore, in this embodiment, the latch output of the latch circuit 201 is further latched by the latch circuit 202 in accordance with the write clock signal WC.

According to such a configuration, as described in the first embodiment, even if the latch output of the latch circuit 201 becomes metastable, the latch output of the latch circuit 202 does not become metastable. . As a result, the external reset signal P7 can be reliably reset.

The latch output of the latch circuit 201 is further supplied to the read clock signal RC by the latch circuit 203.
Latched according to. The latch output is further latched by the latch circuit 204 in accordance with the read clock signal RC. This is because the latch output of the latch circuit 203 may become metastable.

The latch output of the latch circuit 204 is supplied to the read counter 17 via the OR circuit 21. As a result, the read counter 17 is reset to the same value as that at the time of self reset.

[Effects] In this embodiment described in detail above, the same effects as those of the previous embodiment can be obtained, and further, the following effects can be obtained.

(1) First, according to this embodiment, since the width of the active level period of the external reset signal P7 is set to 2 clock width or more, this external reset signal P7 is set to the RS flip-flop circuit. It can be latched without use. This makes it possible to realize an elastic store circuit which is less likely to malfunction due to noise and suitable for verification by a CAD tool.

(2) According to this embodiment, when the external reset signal P7 is latched in accordance with the write clock signal WC, the two latch circuits 201 and 202 sequentially latch the latch signal. Two
Even if the latch output of 01 becomes metastable, the external reset signal P7 can be reliably latched. This is the same when the latch output of the latch circuit 201 is latched according to the read clock signal RC.

(3) Further, according to this embodiment, the reset value of the read counter 17 by the self-reset circuit 18 and the read counter 17 by the external reset circuit 20.
Since the reset value of 1 is set to the same value, the hardware amount of the read counter 17 can be reduced.

[Other Embodiments] The two embodiments of the present invention have been described in detail above.
The embodiment is not limited to the above-described embodiment.

(1) For example, in the above first embodiment, the case where the read counter 17 is reset when the phase difference between the write phase and the read phase of the data D becomes equal to or less than a predetermined value has been described. . However, the present invention may reset the write counter 16. However, in this case, it is necessary to set the width of the high level period and the low level period of the read pulse signal RPi to 2 clock widths or more.

(2) Also, in the second embodiment,
The case where the external reset signal P7 is latched by the write clock signal WC and then by the read clock signal RC has been described. However, according to the present invention, the read clock signal R
After latching by C, it may be latched by the write clock signal WC.

(3) In addition, in the first and second embodiments described above, the case where the clocks are switched using the two latch circuits connected in series has been described. However, in the present invention, the clocks may be replaced by using three or more latch circuits connected in series. in this case,
The final latch output may be used to generate the write phase display signal and the read phase display signal and to reset the counters 16 and 17.

(4) Further, in the first and second embodiments, the case where the present invention is applied to the elastic store circuit has been described. However, the present invention can be applied to a clock transfer circuit other than the elastic store circuit.

(5) In addition, in the first and second embodiments, the case where the present invention is applied to the clock changing circuit for changing the clock in the unit of 1 bit has been described.
However, the present invention can also be applied to a clock crossover circuit that performs clock crossover in units of a plurality of bits.

(6) In addition to this, it is needless to say that the present invention can be variously modified without departing from the scope of the invention.

[0147]

As described above in detail, according to the invention of claim 1, the width of the high level period and the low level period of the write pulse signal for phase comparison is set to 2 clock widths or more, and this write pulse signal is set. Since a self-reset signal is generated by phase comparison after latching with the read clock signal, clocks can be replaced without using the RS flip-flop circuit. As a result, it is possible to provide a clock transfer circuit which is less likely to malfunction due to noise and which is suitable for verification by a CAD tool.

According to the fifth aspect of the invention, the width of the high level period and the low level period of the read pulse signal for phase comparison is set to 2 clock widths or more, and this read pulse signal is latched by the write clock signal. After that, I tried to generate a self-reset signal by phase comparison.
The same effect as the invention according to claim 1 can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the write counter according to the first embodiment.

FIG. 3 is a timing chart showing the operation of the read counter according to the first embodiment.

FIG. 4 is a timing chart showing the operation of the self-resetting circuit of the first embodiment.

FIG. 5 is a block diagram showing a configuration of a second embodiment of the present invention.

[Explanation of symbols]

11 ... Data input terminal 12 ... Data output terminal 13 ... Write clock input terminal 14 ... Read clock input terminal 15 ... Register 16 ... Write counter 17 ... Read counter 18 ... Self reset circuit 19 ... External reset input terminal 20 ... External reset circuit 181 , 182, 183, 201, 202, 203, 2
04 ... Latch circuit 184, 186 ... AND circuit 185, 21 ... OR circuit

 ──────────────────────────────────────────────────の Continued from the front page (72) Inventor Takashi Oya 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd.

Claims (8)

[Claims] 1. Data storage means having a plurality of storage areas, and by dividing the write clock signal, the widths of the high level period and the low level period are both two clock widths or more, and the plurality of storages of the data storage means. Write pulse generation means for generating a plurality of write pulse signals for sequentially writing data in the area, and a plurality of read clock signals of the same frequency that are asynchronous with the write clock signal and are divided into a plurality of data storage means of the data storage means. A read pulse generating means for generating a plurality of read pulse signals for sequentially reading data from the storage area and at least two latch circuits are connected in series, and the plurality of write pulse signals are used as a signal for phase comparison. A latch for sequentially latching selected write pulse signals according to the read clock signal. Switch means and the final latch output of the latch means and the read pulse signal corresponding to the final latch output are compared in phase, and when the phase difference between the two is less than a predetermined value, the read pulse generating means is reset. A clock transfer circuit comprising self resetting means. 2. The self-resetting means latches a final latch output of the latch means in accordance with the read clock signal, and a logical operation of a latch output of the latch circuit and a final latch output of the latch means. A first logic circuit for generating a write phase display signal indicating a write phase of the data, and a plurality of read pulse signals including a read pulse signal corresponding to the final latch output of the latch means, A second logic circuit for generating a reset area display signal indicating a reset area of the read pulse generation means, a write phase display signal generated by the first logic circuit, and a reset area generated by the second logic circuit. A self-reset signal for resetting the read pulse generation means by logically operating a display signal Third clock handoff circuit according to claim 1, characterized in that a logic circuit for generating. 3. An external reset signal, which is constituted by connecting at least two latch circuits in series and whose active level period width is set to 2 clock widths or more, is sequentially latched in accordance with the write clock signal, and is output at the final latch output. The write-side external reset means for resetting the write-pulse generating means and at least two latch circuits are connected in series, and the latch output one stage before the final latch output of the write-side external reset means is used as the read clock. 2. The clock transfer circuit according to claim 1, further comprising a read side external reset means for sequentially latching according to a signal and resetting said read pulse generating means by a final latch output. 4. The reset value of the read pulse generating means by the self resetting means and the reset value of the read pulse generating means by the read side external resetting means are set to be the same value. The clock transfer circuit according to claim 3. 5. A data storage means having a plurality of storage areas, and a plurality of write pulse signals for sequentially writing data in the plurality of storage areas of the data storage means by dividing a write clock signal. By dividing the read clock signal having the same frequency as the write pulse generation means asynchronously with the write clock signal, the widths of the high level period and the low level period are both two clock widths or more, and the plurality of data storage means are provided. A read pulse generating means for generating a plurality of read pulse signals for sequentially reading data from the storage area and at least two latch circuits are connected in series, and the plurality of read pulse signals are used as a signal for phase comparison. A latch for sequentially latching selected read pulse signals according to the write clock signal. Switch means compares the phases of the final latch output of the latch means with the write pulse signal corresponding to the final latch output, and resets the write pulse generation means when the phase difference between the two is less than a predetermined value. A clock transfer circuit comprising self resetting means. 6. The self-resetting means latches a final latch output of the latch means in accordance with the write clock signal, and a logical operation of a latch output of the latch circuit and a final latch output of the latch means. A first logic circuit for generating a read phase display signal indicating a read phase of the data; and a plurality of write pulse signals including a write pulse signal corresponding to the final latch output of the latch means, A second logic circuit that generates a reset area display signal that indicates a reset area of the write pulse generation means, a read phase display signal that is generated by the first logic circuit, and a reset area that is generated by the second logic circuit. A self-reset signal for resetting the write pulse generation means by logically operating a display signal Third logic circuit and a clock handoff circuit according to claim 5, further comprising a generating. 7. An external reset signal, which is constituted by connecting at least two latch circuits in series and has a width of an active level period of 2 clock width or more, is sequentially latched in accordance with the read clock signal, and a final latch output is provided. The read-side external reset means for resetting the read-pulse generating means and at least two latch circuits are connected in series, and the latch output one stage before the final latch output of the read-side external reset means is used as the read clock. 6. The clock transfer circuit according to claim 5, further comprising write-side external reset means for sequentially latching according to a signal and resetting the write pulse generating means with a final latch output. 8. The reset value of the write pulse generating means by the self resetting means and the reset value of the write pulse generating means by the write side external resetting means are set to be the same value. The clock transfer circuit according to claim 7.