JPH0653922A - Phase difference absorbing circuit - Google Patents

Abstract

PURPOSE:To minimize delay amounts from a writing to a reading by deciding the delay amounts of a reading frame pulse by the phase difference of two input data signals or two writing frame pulse signals. CONSTITUTION:This circuit is equipped with a circuit constituted of monostable multivibrators 3 and 4 which detect the phase difference of writing frame pulse signals 103 and 106, and output a delayed writing frame pulse signal 113, AND circuits 5 and 6, and OR circuit 7, and a delay circuit 8 which delays the writing frame pulse signal 113 only in a delay time equal to the specific delay amounts between the writing and the reading in an elastic storage memory. The output signal 114 of the delay circuit 8 is inputted to each elastic storage memory as the reading frame pulse signal. The delay amounts of the elastic storage memory are decided by the phase difference of the writing frame pulse signals 103 and 106, and the delay time specific to the elastic storage memory.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase difference absorption circuit and, more particularly, to a phase synchronization circuit of a time division multiplexer.
The present invention relates to a phase difference absorption circuit that absorbs a phase difference between two signals.

[0002]

2. Description of the Related Art As a conventional phase difference absorption circuit, there is a phase difference absorption circuit using an elastic store memory. FIG. 4 is a block diagram of a conventional example, and FIG. 5 is a timing chart for explaining the operation of FIG.

The operation of the conventional example will be described below with reference to FIGS. The write frame pulse signal 203 and the write frame pulse signal 206 are used as triggers to write the input data 201 and the input data 204 to the elastic store memory 21 and the elastic store memory 22, respectively, and the read frame pulse signal 214 is used as a trigger. Data is read from the elastic store memory 21 and the elastic store memory 22 and output as output data 202 and output data 205.

At this time, the timing of the read frame pulse is set so that the phase difference between the input data 201 and the input data 204 has a sufficient margin and the data is read from the elastic store memory.

[0005]

As described above, in the conventional phase difference absorption circuit, the timing of reading from the elastic store memory should have a sufficient margin in order to prevent the read omission or double reading of the written contents. Therefore, there is a problem that the delay time is longer than necessary.

[0006]

In the phase difference absorption circuit of the present invention, the first error data is output by reading the first input data by the first write frame pulse and writing the read data by the read frame pulse. A stick store memory, a second input data is written by a second write frame pulse, a second elastic store memory is read by the read frame pulse and is output as second output data, and the first write frame is written. A first monostable multivibrator which inputs a pulse and outputs a pulse having a predetermined time width T1, and a second monostable multivibrator which inputs the second write frame pulse and outputs a pulse having the time width T1. And the first write frame pulse and the first write frame pulse.
And a first AND circuit that inputs the output pulse of the second monostable multivibrator, the second write frame pulse, and the output pulses of the first and second monostable multivibrator. A second AND circuit for inputting the output pulses of the first and second AND circuits, and a delay for delaying the output pulse of the OR circuit by a predetermined time width T2 and outputting the read frame pulse. And a circuit.

[0007]

Next, an embodiment of the present invention will be described with reference to the drawings. 1 is a block diagram of the present embodiment, and FIGS. 2 and 3 are timing charts for explaining the operation of FIG.

The elastic store memory 1 uses the write frame pulse signal 103 as a trigger to input data 10
1 is written to the elastic store memory 2
Writes the input data 104 using the write frame pulse signal 106 as a trigger.

The monostable multivibrator 3 receives the write frame pulse signal 103 and has a constant time width (T1).
The pulse signal 109 is output. The constant time width (T1) in this case is the time obtained by adding the maximum expected phase difference (T3) between the write frame pulse signals 103 and 106 and the pulse width (T4) of the write frame pulse signal. To do. Further, the monostable multivibrator 4 inputs the write frame pulse signal 106 and outputs a pulse signal 110 having a constant time width (T1).

The AND circuit 5 is an AND circuit that takes the logical product of the output signals 109 and 110 and the write frame pulse signal 103, and the AND circuit 6 is the output signal 109 and output signal 110 and the write frame pulse signal. AND with 106. Here, as shown in FIG. 2A, the write frame pulse signal 109 is the write frame pulse signal 1
When the delay amount is larger than 10, the AND circuit 6 outputs the write frame pulse signal 106 as the output signal 112 (the output signal 111 remains at the “L” level), and conversely. When 103 has a large delay amount with respect to the write frame pulse signal 106, the output signal 11
The write frame pulse signal 103 is output at 1 (the output signal 112 remains at the “L” level).

When the write frame pulse signal 103 and the write frame pulse signal 106 have the same delay amount as shown in FIG. 3, the output frame 111 is the write frame pulse signal 103 and the output frame 112 is the output signal 112. The write frame pulse signal 106 is output respectively. The OR circuit 7 is an OR circuit that takes the logical sum of the output signals 111 and 112.
13 is outputted, and the delay circuit 8 gives the signal 113 a delay of a minimum required time (T2) from writing the data in the elastic store memory 1 or 2 to reading the data and outputting the signal 113. .

The elastic store memories 1 and 2 are
Data is read by using the output signal 114 from the delay circuit 8 as a read frame pulse signal, and the output data 10 having the same phase is output.
2 and 105 are output respectively.

[0013]

As described above, according to the present invention, the delay time from the writing to the reading of two input data having a phase difference and the delay peculiar to the elastic store memory and the phase difference between the two write frame pulses at that time is determined. Since the amount, that is, the minimum required time from writing to reading is added, there is an effect that the delay amount is reduced to the minimum required as compared with the conventional example in which a constant delay time with a margin in advance is provided.

[Brief description of drawings]

FIG. 1 is a block diagram of one embodiment according to the present invention.

2A is a timing chart in the case where the input signals in FIG. 1 have a phase difference, and FIG. 2B is a timing chart in the case where there is no phase difference.

FIG. 3 is a timing chart of input / output signals in FIG.

FIG. 4 is a block diagram of a conventional example.

5 is a timing chart of input / output signals in FIG.

[Explanation of symbols]

 1 elastic store memory 2 monostable multivibrator 3 monostable multivibrator 4 AND circuit 5 OR circuit 6 delay circuit 7 AND circuit 8 elastic store memory B 101 input data 104 input data 103 write frame pulse signal 106 write frame pulse Signal 107 write clock 102 output data 109 output signal of monostable multivibrator 3 110 output signal of monostable multivibrator 4 111 output signal of AND circuit 112 output signal of AND circuit 6 113 output signal of OR circuit 7 114 read frame Pulse signal 105 Output data 108 Read clock

Claims (2)

[Claims] 1. A first elastic store memory for outputting first input data as a first output data read by a write / read frame pulse by a first write frame pulse, and a second input data as a second output data. Write by the write frame pulse of, and read by the read frame pulse, the second elastic store memory which outputs as the second output data, and the first write frame pulse, and outputs a pulse of a predetermined time width T1. A first monostable multivibrator, a second monostable multivibrator which inputs the second write frame pulse and outputs a pulse of the time width T1, the first write frame pulse and the first monostable multivibrator. 1 and an output pulse of the second monostable multivibrator, and a second AND circuit
Second AND circuit for inputting the write frame pulse and the output pulse of the first and second monostable multivibrators, and an OR circuit for inputting the output pulse of the first and second AND circuits. , A delay circuit that delays the output pulse of the OR circuit by a predetermined time width T2 and outputs the delayed frame pulse as the read frame pulse. 2. The time width T1 is an expected phase difference between the first write frame pulse and the second write frame pulse and a pulse width of the first or second write frame pulse. 2. The time width T2 is set to be a minimum time required from the writing of data to the reading of data by the first or second elastic store memory. The described phase difference absorption circuit.