JPS62250583A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To attain a high-speed memory by specifying the setup time and write pulse width by a delay time of a memory IC inside and a logical gate or the like. CONSTITUTION:In supplying a low-level write control signal WE externally at data writing, the write control signal WE is fetched in a latch circuit LT by using a signal retarding a clock CLK by a delay circuit DLY1. A signal B having the same phase as that of the write signal WE and a signal A having opposite phase are outputted from the latch circuit LT and the signal B is retarded by a delay circuit DLY2. Then the retarded signal B' is fed to an AND gate G together with the opposite phase signal A, they are ANDed to form an internal write pulse WP. The internal write pulse WP formed in this way is fed to a write amplifier WA.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a technology that is effective when applied to semiconductor integrated circuit technology and a data write control method in semiconductor storage devices, such as internal write in ultra-high-speed static RAM. This invention relates to techniques that are effective in forming control signals.

[Prior Art] In a conventional static RAM, as shown in FIG. 3, the changeable cycle time Tcyc of the address signal ADD is changed to the set-up time ts^, the hold time tH^, and the pulse width necessary for writing. Data writing is executed by externally applying a write pulse WE specified to have tw (Asakura Shoten Co., Ltd., published June 30, 1981, (Refer to page 331 of “Application Handbook”).

[Problem that the invention attempts to solve] In a static RAM like the one mentioned above.

If you try to shorten the write cycle Tcyc to increase speed, you will need a very narrow pulse width tw, and
Setting the timing of the write pulse WE also becomes difficult. Therefore, it is very difficult to generate such a write pulse externally, which poses a problem in that it imposes a heavy burden on the user.

An object of the present invention is to shorten the write cycle without making it difficult to set the timing of a write control signal supplied from the outside, thereby increasing the speed of the memory.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, it includes a latch circuit that latches an address signal and a write control signal supplied from the outside, a delay circuit, and a logic gate, and a signal forming circuit that forms an internal write pulse based on the latched write control signal. It is.

[Function] According to the above-mentioned means, the set-up time and write pulse width are defined by the delay time inside the memory IC and the logic gate, etc., which makes it difficult to set the timing of the write control signal supplied from the outside. The above objective of increasing the speed of the memory by shortening the write cycle without causing any problems can be achieved.

[Example] Figure 1 shows a bipolar static RAM according to the present invention.
An example in which the method is applied to is shown.

In this embodiment, the address signal AD supplied from the outside is
An address latch circuit ALT that latches D and a latch circuit LT that latches write control signal WE are provided. Although the address signal ADD is not particularly limited, the address signal ADD is captured in synchronization with the fall of a clock CLK supplied from the outside, and the captured address signal is supplied to the decoder DEC. The decoder DEC decodes the supplied address signal to address the memory array MA.
A selection signal that selects one of the memory cells is formed and output.

As a result, the information of the selected memory cell in memory array MA is read out, supplied to sense amplifier SA, amplified, and output from output buffer DOB to the outside.

On the other hand, when writing data, when a low-level write control signal WE is supplied from the outside at the timing shown in FIG.
It is taken into T.

Then, the latch circuit LT outputs a signal B having the same phase as the write signal WE and a signal A having the opposite phase, of which the signal B having the same phase is delayed by the delay circuit DLY2. and,
The delayed signal B' is supplied to the AND gate G together with the signal A of the opposite phase, and the internal write pulse WP is formed by ANDing the two signals. The formed internal write pulse WP is supplied to the write amplifier WA.

Then, the write amplifier WA is driven, and a pair of complementary write data signals corresponding to the input data Din input from the outside to the data input buffer DIR are formed and supplied to the memory array MA.
Data is written to the memory cell selected by the EC. The latch circuit LT must be set in preparation for the next cycle of writing.

For this set signal, the signal B' is connected to the delay circuit DLY3.
Using the delayed signal C, the latch circuit LT is set. (Delay time t s e t) As a result, the signal A falls and returns to a steady state.

In the above embodiment, the delay caused by the delay circuit DLY1, that is, the latch point of the address signal (clock CL
The set-up time tS^ is determined by the delay time of the write pulse WP from the rising edge of K. Furthermore, the pulse width tw of the write pulse WP is determined by the delay time caused by the delay circuit DLY2. Furthermore, the hold time tHA is set as the remaining time after subtracting the sum of the set-up time ts^ and the pulse l[tw from the cycle Tcyc of the clock CLK that determines the memory cycle.

As described above, in the above embodiment, a latch circuit for the address signal ADD and the write control signal WE is provided in the static RAM, and the write pulse is generated inside the memory, so the timing of the write control signal WE to be generated externally is set. The conditions to do so will be relaxed. Along with this, the pulse width tw
Since the memory can be made narrower internally than when it is made externally, the memory cycle can be shortened and the writing speed can be increased accordingly.

Moreover, in conventional static RAM, in order to remove noise from write pulses supplied from the outside,
A circuit called a two-stage shrink circuit was provided, but in the above embodiment, the delay circuit DLY2 and the AND gate G have a function of cutting noise on the write control signal WE, so the two-stage shrink circuit is also unnecessary. Become.

Note that the delay circuits DLY1 and DL in the above embodiments
Y2 can be configured to have a desired delay time by connecting an appropriate number of NAND gates and NOR gates.

Further, the delay circuit DLYI can be omitted by positively providing a difference in gate delay time between the address latch circuit ALT and the write control signal latch circuit LT.

As explained above, the above embodiment includes a latch circuit that latches an address signal and a write control signal supplied from the outside, a delay circuit, and a logic gate, and generates an internal write pulse based on the latched write control signal. Since a signal forming circuit is provided for forming a write control signal, the setup time and write pulse width can be set by the delay time inside the memory IC and the logic gate, etc., making it difficult to set the timing of the write control signal supplied from the outside. The effect is that the write cycle can be shortened and the speed of the memory can be increased without any problems.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above example,
Although a latch circuit ALT for latching the address signal is provided, the address latch circuit can be omitted if an address signal whose timing is set fairly well in relation to the clock CLK is input.

The above explanation will mainly focus on the delay circuit DLY, which is the field of application that was the background of the invention made by the present inventor.
Although the present invention has been described as being applied to semiconductor memory devices in general, the present invention is not limited thereto.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, it is possible to shorten the write cycle and increase the speed of the memory without making it difficult to set the timing of the write control signal supplied from the outside.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention applied to a bipolar static RAM, FIG. 2 is a timing chart during writing, and FIG. 3 is an address signal and write control signal in a conventional static RAM. It is an explanatory diagram showing the timing. ALT...Address latch circuit, MA...Memory array, DLYI, DLY2. DLY3...Delay means (delay circuit), LT...Latch circuit for write control signal, WA...Write amplifier.

Claims (1)

[Claims] 1. A semiconductor memory device capable of reading and writing data at any time based on an address signal and a control signal supplied from the outside, comprising a latch circuit that can take in the address signal. , comprising a latch circuit that can take in a write control signal, a means for delaying the write control signal latched by the latch circuit, and a signal forming circuit that internally forms a write control pulse signal. semiconductor storage device. 2. The semiconductor memory circuit according to claim 1, further comprising delay means for shifting the latch timing of each signal taken into the two latch circuits by a setup time.