KR100585085B1 - Data transmission circuit in data read path of high speed memory device - Google Patents

Abstract

A data transfer circuit provided in a data read path of a high speed memory device is disclosed. A data transfer circuit provided in a data read path of a high speed memory device according to the present invention is a data transfer circuit provided in a read path of a high speed memory device having a pipelined structure, and receives input data in response to a predetermined clock signal. At least one tri-state buffer latch circuit for buffering and latching, wherein the tri-state buffer latch circuit inputs a clock signal and an inverted clock signal as a control signal, and inverts and buffers the input data in response to the control signal. And latching output signals of the inverter and the tri-state inverter and outputting latched data when the output of the tri-state inverter is floated.

According to the present invention, by implementing a tri-state buffer with a minimum delay in the data read path of a high-speed memory device having a pipelined structure, skew between data can be minimized, and stable high speed can be achieved without damaging the data. The effect is that data transfer can be performed.

Description

Data transmission circuit in a data read path of a high speed memory device TECHNICAL FIELD

1 is a circuit diagram showing a data transfer circuit provided in a conventional data read path.

2 is a circuit diagram illustrating a data transfer circuit provided in a data read path of a high speed memory device according to the present invention.

3 is a diagram illustrating an embodiment of a pipeline structure of a high speed memory device to which a data transfer circuit according to the present invention is applied.

4 is a circuit diagram illustrating an embodiment in which a data transmission circuit according to the present invention is applied to a double data rate DRAM.

5A to 5G are waveform diagrams showing the operation of the circuit shown in FIG.

The present invention relates to a semiconductor memory device, and more particularly, to a data transfer circuit provided in a data read path of a high speed semiconductor memory device.

In general, a read operation of reading data from a dynamic random access memory (RAM) may be performed by CAS latency (LATENCY). That is, the CAS latency is not output immediately after the read command, but is output with a predetermined time latency by the internal control signal. In particular, in the case of a high speed DRAM such as a double data rate DRAM, the data read operation is effectively performed by the pipeline structure. As such, when reading data by the pipeline structure, a difference occurs in the transmission speed depending on how the data is transmitted. Therefore, in order to effectively transfer data in clock cycles as the DRAM speeds up, a transmission scheme is very important.

1 is a circuit diagram illustrating a data transfer circuit provided in a conventional data read path, and is implemented as a tristate buffer latch. Referring to FIG. 1, the tri-state buffer latch includes an inverter 10, a transfer gate TG11, and a latch 15.

The inverter 10 inverts the input data applied from the data input terminal DBin and outputs the inverted result. The transfer gate TG11 transfers inverted input data through the data output terminal DBout in response to the clock signal CLK and the inverted clock signal CLKB. That is, when the clock signal CLK is at the high level, data having a high or low level is transferred through the output terminal DBout. On the other hand, when the clock signal CLK is at the low level, the transfer gate TG11 is not turned on and its output is in a floating state. At this time, previous data stored in the latch 15 is transferred through the data output terminal DBout. Is output.

However, in the conventional three-state buffer latch circuit as shown in FIG. 1, the output of the inverter 10 is not directly connected to the output of the latch 15, but is connected through the transmission gate TG11. Therefore, the skew (SKEW) at the time of data output by the transmission delay time due to the transmission gate (TG11) can be increased to affect subsequent data.

As a result, the data transfer circuit implemented by the tri-state buffer latch shown in FIG. 1 has a problem that the high speed transfer can be prevented due to skew of output data.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a data transfer circuit provided in a data read path of a high speed memory device that enables high speed transfer by minimizing skew between output data in a read path of a high speed memory.

In order to achieve the above object, a data transfer circuit provided in a data read path of a high speed memory device according to the present invention is a data transfer circuit provided in a read path of a high speed memory device having a pipelined structure. At least one tri-state buffer latch circuit for buffering and latching in response to a clock signal of the circuit, wherein the tri-state buffer latch circuit inputs a clock signal and an inverted clock signal as a control signal, and inputs data in response to the control signal. And a latch for outputting the output signal of the tri-state inverter and the tri-state inverter, and outputting the latched data when the output of the tri-state inverter is floated.

Hereinafter, a data transfer circuit provided in a data read path of a high speed memory device according to the present invention will be described with reference to the accompanying drawings.

2 is a circuit diagram illustrating a data transfer circuit included in a data read path of a high speed memory device according to an exemplary embodiment of the present invention. Referring to FIG. 2, the data transfer circuit includes a tri-state inverter 20 and a latch 25.

The tri-state inverter 20 of FIG. 2 is composed of PMOS transistors MP21 and MP22 and NMOS transistors MN21 and MN22. Here, the PMOS transistors MP21 and MP22 are connected in series between the power supply voltage VDD and the data output terminal DBout, and the NMOS transistors MN21 and MN22 are connected in series between the data output terminal DBout and the ground potential VSS. Connected. The gate of the PMOS transistor MP21 is connected to the inverted clock signal CLKB, the source is connected to the power supply voltage VDD, and the drain is connected to the source of the PMOS transistor MP22. The gate of the PMOS transistor MP22 is connected to the data input terminal DBin, and the drain thereof is connected to the data output terminal DBout. In addition, the gate of the NMOS transistor MN21 is connected to the data input terminal DBin, the drain is connected to the data output terminal DBout, and the source is connected to the drain of the NMOS transistor MN22. The gate of the NMOS transistor MN22 is connected to the clock signal CLK, and the source thereof is connected to the ground potential VSS.

The three-state inverter 20 having the above configuration inputs the clock signal CLK and the inverted clock signal CLKB as a control signal, respectively, inverts and buffers the input data, and converts the inverted data into the data output terminal DBout. Output through That is, the three-state inverter 20 may obtain an output having three states of high level, low level, and floating state according to the state of the clock signal CLK.

The latch 25 consists of inverters 22, 24 connected in series. At this time, the latch 25 has an input and an output connected to the data output terminal DBout to latch the output of the tri-state inverter 20. That is, the latch 25 outputs the latched data through the data output terminal DBout when the output of the inverter 20 is floated.

Specifically, the operation of the data transfer circuit shown in FIG. 2 will be described in detail. That is, when the clock signal CLK input as the control signal is at a high level, the PMOS transistor MP21 and the NMOS transistor MN22 are turned on. At this time, for example, when the data input DBin is at the high level, the NMOS transistor MN21 is turned on and the data output through the data output terminal DBout is at the low level. In addition, if the data input through DBin is at the low level while the clock signal CLK is at the high level, the PMOS transistor MP22 is turned on and the output data is at the high level.

However, when the clock signal CLK is at the low level, neither the PMOS transistor MP21 nor the NMOS transistor MN22 is turned on, and the output of the three-state inverter 20 is in a high impedance state, that is, a floating state. Therefore, in this case, the previous data stored in the latch 25 is output through the data output terminal DBout.

That is, as shown in FIG. 2, the present invention can minimize the time delay during data transmission by implementing a buffer using a three-state inverter without using a transmission gate.

FIG. 3 is a diagram illustrating an exemplary pipelined structure of a high speed memory device to which the data transfer circuit shown in FIG. 2 is applied. The data transfer circuit includes three state buffer latches 310, 320, and 330 connected in series. In the example of FIG. 3, the CAS latency LATENCY is assumed to be three.

Referring to FIG. 3, the tristate buffer latch 310 includes a tristate inverter 312 and a first latch 314. The three-state inverter 312 inverts and buffers the input data IN by inputting the first clock signal CLK1 and the inverted first clock signal CLKB1 as a control signal. The first latch 314 latches the output signal of the tri-state inverter 312 and outputs the latched signal when the output signal of the tri-state inverter 312 is in the floating state. At this time, the output signal D1 of the tri-state buffer latch 310 is applied to the input of the tri-state buffer latch 320.

The configuration and operation of the other three-state buffer latches 320 and 330 are similar to those of the three-state buffer latch 310, and thus detailed description thereof will be omitted. However, the three state buffer latches 320 and 330 are different only in that they operate by the second clock signal CLK2 and the third clock signal CLK3.

That is, as shown in FIG. 3, in order to prevent continuous data from being corrupted in a high-speed memory device having a pipelined structure whose operation is controlled by CAS latency, such as synchronous DRAM (hereinafter referred to as SDRAM), The method of latching the previous data and delivering the next data is used. In addition, the same method is used for synchronous graphic RAM (hereinafter, referred to as SGRAM), and in case of SGRAM requiring higher speed, data skew cannot be ignored. Especially in the case of DDR DRAM, skew during data transfer is considered very important.

4 is a circuit diagram illustrating an embodiment in which a data transfer circuit according to the present invention is applied to a DDR DRAM. Referring to FIG. 4, the data transfer circuit is composed of three state buffer latches 40 and 42, an inverter 48 and a three state inverter 46.

The tri-state buffer latch 40 buffers and latches the first input data DBin_F in response to the first transmission clock signal CLK_F and the inverted first transmission clock signal CLK_FB, and outputs the result thereof to the output terminal DBout. Output through For this operation, the tri-state buffer latch 40 is composed of a tri-state inverter 400 for inverting and buffering input data, and a latch 410 for latching the output of the tri-state inverter 400. In the embodiment of FIG. 4, the tri-state inverter 400 includes PMOS transistors MP41 and MP42 and NMOS transistors MN41 and MN42, and the latch 410 includes inverters 412 and 414 connected in series. do. Here, the first transmission clock signal CLK_F is defined as a clock signal generated in synchronization with a first edge of the clock signal CLK, for example, a rising edge, and CLK_FB is defined as an inverted clock signal of CLK_F. . In addition, the clock signal CLK may be CLK1, CLK2 or CLK3 when the pipeline structure in FIG. 3 is taken as an example.

The tri-state buffer latch 42 buffers and latches the second input data DBin_S in response to the first transmission clock signal CLK_FB inverted from the first transmission clock signal CLK_F and outputs the result of the inverter 48. To the input of). For this operation, tri-state buffer latch 42 is composed of tri-state inverter 420 and latch 440. Here, the tri-state inverter 420 is composed of PMOS transistors MP43 and MP44, and NMOS transistors MN43 and MN44, and the latch 440 is composed of inverters 442 and 444 connected in series.

The inverter 48 inverts the output of the tri-state buffer latch 420 and outputs the inverted result.

The tri-state inverter 46 applies the output signal of the inverter 48 to the data input, and inverts and buffers the input data in response to the second transmission clock signal CLK_S and the inverted second transmission clock signal CLK_SB. . For this operation, the tri-state inverter 46 is composed of PMOS transistors MP46 and MP47 and NMOS transistors MN46 and MN47. Here, the second transmission clock signal CLK_S is a signal generated in synchronization with a second edge of the clock signal CLK, for example, a falling edge, and CLK_SB is defined as an inverted clock signal of CLK_S.

5 (a) to 5 (g) are waveform diagrams for explaining the operation of the circuit shown in FIG. 4, FIG. 5 (a) shows a clock signal CLK, and FIG. The transfer clock signal CLK_F is shown, FIG. 5C shows the second transfer clock signal CLK_S, FIG. 5D shows the first input data DBin_F, and FIG. 5E shows the second. The input data DBin_S is shown, FIG. 5 (f) shows the output data DBout, and FIG. 5 (g) shows the actual form of the output data DBout shown in FIG. 5 (f).

4 and 5, the operation of the data transfer circuit shown in FIG. 4 is described in detail. First, it is assumed that the clock signal serving as a reference for data reading is the clock signal CLK of FIG. As described above, CLK_F in FIG. 5 (b) is generated in synchronization with the rising edge of the clock signal CLK shown in FIG. 5 (a), and CLK_S in FIG. 5 (c) is synchronized with the falling edge of CLK. Is generated. In addition, the first input data DBin_F and the second input data DBin_S are input in parallel through an I / O line, as shown in FIGS. 5 (d) and 5 (e), respectively, and have a high level and a low level, respectively. It is assumed to be data with levels.

At this time, the first input data DBin_F and the second input data DBin_S of FIGS. 5D and 5E are each in three states at the time when the first transmission clock signal CLK_F rises to a high level. The inverters 400 and 420 are inverted and output. That is, referring to FIG. 5 (f), at the time when the first transmission clock signal CLK_F of FIG. 5 (b) rises, inverted first input data, that is, low level data, is output through the data output terminal. . Here, the latch 410 latches the inverted first input data DBin_F, and outputs the latched signal through DBout when the transmission clock signal CLK_F becomes low. Similarly, the latch 440 latches the inverted second input data DBin_S in the tri-state inverter 420, and outputs the inverted second input data when the first transmission clock signal CLK_F becomes low. Here, the signal latched in the third state buffer latch 42 is input to the inverter 48, inverted in the inverter 48, and then input to the three state inverter 46. That is, the tri-state inverter 46 outputs inverted data of the second input data DBin_S through the output terminal DBout at the time when the second clock signal CLK_S of FIG. 5C becomes high level. ) That is, referring to FIG. 5 (f), it can be seen that inverted first input data is output at the time when CLK_F rises, and then inverted second input data is output at the time when CLK_S rises. In other words, each data bit is transferred in parallel in the data read path of the DDR DRAM, and the serial signals are generated by the clock signals CLK_F and CLK_S generated in synchronization with the rising and falling edges of the clock signal CLK. Is converted to.

In actual data transfer, the data output through the data output terminal DBout of FIG. 5 (f) has a skew as shown in FIG. 5 (g). In the present invention, as described above, the transmission speed may be improved by minimizing the amount of skew. In other words, the skew should be minimized in order to ensure that data is continuously transmitted without being damaged within 1/2 time of a short clock cycle.

According to the present invention, by implementing a tri-state buffer with a minimum delay in the data read path of a high-speed memory device having a pipelined structure, skew between data can be minimized, and stable high speed can be achieved without damaging the data. The effect is that data transfer can be performed.

Claims (3)

In a data transfer circuit provided in a read path of a high speed memory device having a pipeline structure, At least one tri-state buffer latch circuit for buffering and latching input data in response to a predetermined clock signal, The three-state buffer latch circuit, A three-state inverter that inputs the clock signal and the inverted clock signal as a control signal and inverts and buffers the input data in response to the control signal; And And a latch for latching an output signal of the tri-state inverter and outputting the latched data when the output of the tri-state inverter is floated. The method of claim 1, wherein the three-state inverter, Transistors having the input data and the clock signal as gate inputs are respectively connected in series between the data output terminal and the ground potential, and gate input the input data and the inverted clock signal between a power supply voltage and the data output terminal. And the transistors are connected in series. The method of claim 1, The control signal of the three-state inverter is at least one of a first transmission clock signal and a second transmission clock signal generated in synchronization with the rising edge and the falling edge of the clock signal, And the input data is a predetermined bit of data input in parallel.

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