JPS6150428B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a vertical synchronization detection circuit that extracts a vertical synchronization pulse from a composite synchronization pulse train separated from a television signal.

A conventional circuit for detecting a vertical synchronizing pulse from a composite synchronizing pulse in a television receiver or the like is shown in FIG. That is, a composite synchronizing pulse is applied to the input terminal 11, and the applied signal is applied to the integrator circuit 12.
The voltage is applied to the voltage comparator circuit 13 via the voltage comparator circuit 13. Since the pulse width is small during the horizontal pulse or equivalent pulse period, the voltage obtained from the integrating circuit 12 cannot exceed the voltage level set in the voltage comparator circuit 13. However, when a vertical synchronizing pulse with a large pulse width as shown in FIG. 2a is applied, an output as shown in FIG. Here, the output voltage of the integration circuit 12 is compared with the voltage level set in the voltage comparison circuit 13, as shown in FIG. 2c, and there is a section in which it exceeds a threshold value. During this period, a vertical synchronizing pulse as shown in FIG.

According to the above-described conventional vertical synchronization detection means, even in today's world where integrated circuits are popular, it is still difficult to integrate them. This is because it is difficult to create a capacitor with high precision and a large capacitance within an integrated circuit, and adding a capacitor outside the integrated circuit requires an increase in the number of pins in the circuit. This is because there is a restriction.

The present invention has been made to address the above-mentioned circumstances, and aims to provide a vertical synchronization detection circuit that is suitable for integration into an integrated circuit and that obtains phase-stable pulses without being affected by noise. purpose.

Embodiments of the present invention will be described below with reference to the drawings. That is, in FIG. 3, 21 is an input terminal to which a composite video signal is applied, and is connected to a synchronization separation circuit 22. This synchronization separation circuit 22 separates synchronization signals, and an output terminal from which a composite synchronization pulse is obtained is connected to an up-down counter 23 and an up-down switching terminal 24. The up-down counter 23 has flip-flop circuits F ₁ to _{F o} provided in multiple stages. A clock pulse input terminal _Cp is set at the clock terminal of the first stage flip-flop circuit _F1 . The connection structure of the flip-flop circuit, representing the first stage and the second stage, is as follows. The non-inverting output terminal Q ₁ of the flip-flop circuit F ₁ is connected to the first input terminal of the AND circuit AG ₁ and also to the input terminal of the NAND circuit 26. Further, the inverting output terminal ₁ of this flip-flop circuit F ₁ is connected to the first input terminal of the AND circuit DG ₁ and also to the input terminal of the NAND circuit 27 . Further, the up-down switching terminal 24 is connected to a second input terminal of the AND circuit AG ₁ , and the up-down switching terminal 24 is connected to a second input terminal of the AND circuit DG ₁ via an inverter NT. . And the said AND circuit
The output terminals of AG ₁ and DG ₁ are the first and second terminals of OR circuit OR ₁ .
connected to each input terminal. The output terminal of this OR circuit OR ₁ is a flip-flop circuit.
Connected to the clock input of _F2 . The second and third stages, and the third and fourth stages are successively connected using the same connection circuit configuration as the flip-flop circuits F ₁ and F ₂ above, and the flip-flop circuit F _o in the final stage is connected in sequence. The inverted output terminal _Qo is connected to the input terminal of the NAND circuit 26, and the inverted output terminal is connected to the NAND circuit 2.
It is connected to the input terminal of 7. Further, the up/down switching terminal 24 is connected to the input terminal of the NAND circuit 26, and the inverter
It is connected to the input end of the NAND circuit 27 via NT.

The output logic value of the NAND circuit 26 is set by each logic of the non-inverting output terminals Q ₁ -Q _o of the flip-flop circuits F ₁ -F _o and the up/down switching terminal 24. The output logic value is set by each logic of the inverting output terminals ₁ to _o of the circuits F ₁ to F _o and the inverter NT. the NAND circuit 26,
The output terminal of 27 is connected to the first and third input terminals of an AND circuit 28, and the output terminal of this AND circuit 28 is connected to the clock pulse input terminal 25.
It is connected to the.

Furthermore, the second input terminal of the AND circuit 28 is connected to the output terminal of a clock pulse generation circuit 29. The flip-flop circuits F ₁ to F _o
The non-inverting output terminals Q ₁ to _{Q o} are also connected in parallel to one input terminal of the comparator circuit 35 . The other input terminal of this comparison circuit 35 is set with predetermined data to be compared. This comparison circuit 35 derives a rising pulse when the output state (data) from the up-down counter 23 becomes larger than the set data (number), and its output terminal is connected to the counter circuit 3.
6. This counter circuit 36 is
When the output pulse from the comparator circuit 35 continues for a certain period of time after the output pulse rises, the vertical synchronizing pulse is output to the output terminal 3.
In order to obtain the generation timing, the output terminal of the clock pulse generation circuit 29 is also connected to the clock input terminal.

The vertical synchronization detection circuit according to the present invention is constructed as described above.Next, the functions and operations of each part will be explained with reference to the waveform diagram of FIG. 4. First, the up-down counter 23 is switched between up-counting and down-counting functions by a composite synchronization pulse applied to its up-down switching terminal 24. In other words, up-counting is performed during the horizontal sync pulse section (5.1 μs), equalization pulse section (about 2.5 μs), and vertical sync pulse section (about 29.3 μs) (high level), and down counting is performed during other sections (low level). It is something that takes action. This means that when a pulse is applied to the switching terminal 24 and the logic is 1, the non-inverting output terminals Q ₁ to Q _o
AND circuits connected to each side AG ₁ ~
When the gate of AG _o-1 is opened and counting up, and the switching terminal 24 is logic 0, the inverted output terminal ₁ ~ _o
AND circuits connected to each side DG ₁ ~
By counting down by opening the gate of DG _o-1 via inverter NT.

When the synchronization pulse is logic 1 and up count,
All logic inputs to the NAND circuit 26 are "1"
When this occurs, the output logic of the NAND circuit 26 becomes "0" and the gate of the AND circuit 28 is closed, so that no clock pulse is applied to the counter and its output state is maintained. Furthermore, when the synchronization pulse is 0 and the count is down, when all the logic inputs to the NAND circuit 26 become "0", all the logic inputs to the NAND circuit 27 become "1", and the output of this NAND circuit 27 becomes a logic 0, closing the gate circuit 28 and stopping the counting operation of the counter. Therefore, the NAND circuit 26,
27, AND circuit 28, etc. form a counter overflow/underflow prevention circuit.

Next, the operation during the horizontal synchronization pulse period (approximately 5 μs) will be explained. In this case, the up/down switching terminal 24 is at the logic of synchronous pulse "1". Now, assuming that the period of the output of the clock pulse generating circuit 29 is, for example, 1 μs, the counter 23 counts up 5 clocks. This counted binary code is applied to a comparison circuit 35.
Next, the switching terminal 24 becomes logic 0, and the gates of the AND circuits DG ₁ to _{DG o-1} provided on the inverting output terminal side are opened. This results in a down-count function, and the count for the aforementioned 5 clocks is counted down. At this time, the input terminals of the NAND circuit 26 are all 0, and the input terminals of the NAND circuit 27 are all 1, so that the underflow prevention function is activated.
When the horizontal period passes and the next horizontal synchronization pulse comes, the above-described operation is repeated. Therefore, the up and down counting operation period of the counter 23 is 10 .mu.s each time one horizontal synchronizing pulse is added, as shown in period T1 in FIG. Here, the output (rising pulse) of the comparison circuit 35 is 2
If it were to occur from the 2nd clock, it would occur from the 2nd clock to the 3rd, 4th, 5th, 6th, 7th, 8th, and 9th clock. In other words, the comparison circuit 35
The comparison code set to 2 is a code corresponding to 2 clocks, and is set so that a rising pulse can be obtained if there are more input codes than this. Due to the above rising pulse,
When the counting operation of the counter circuit 36 is started, this counter counts up to 8 clocks. In this case, the counter circuit 36 is set so as not to derive a vertical output pulse unless the clock pulse is counted for one horizontal period or more (approximately 64 μs=64 clocks). Therefore, at the output terminal 37, in the above-mentioned horizontal synchronizing pulse part,
A detection pulse, ie, a vertical output pulse, cannot be obtained.

Next, the operation in the equivalent pulse portion will be explained. The pulse width of the equivalent pulse is approximately 2.5 μs,
During the period when the up-down counter 23 is operating, as shown in period T2 in FIG.
The total time including the down count is approximately 5 μs. In this case as well, the output pulse width of the comparator circuit 35 is insufficient as in the case when the previous horizontal synchronizing pulse arrived, and no vertical pulse appears at the output terminal 37.

Next, the operation in the vertical synchronization pulse section will be explained. The pulse width of the vertical synchronization pulse is approximately 29.3μs
There is a gap of about 2.5 μs, and this occurs repeatedly six times (for three horizontal line periods). After this, the pulse width is approximately 2.5μs, and the pulse interval is approximately
An equivalent pulse portion of 29.3 μs arrives. In the vertical synchronization pulse part, the up-down counter 23
will count up about 29.3 μs, then about 2.5
The operation (approximately 181 μs) is repeated by down-counting μs, then up-counting approximately 29.3 μs, and down-counting approximately 2.5 μs. Therefore, the number of data that is up-counted and added to the comparison circuit 35 is sequentially increased, and the period of the rising pulse derived from this comparison circuit 35 is 65μ.
Continues for more than s. As a result, the counter circuit 3
From 6 onwards, the vertical detection pulse is activated after 65 μs (period
T3), the signal is further output for about 180 μs. According to the vertical pulse separation means that operates in this manner, the integral value of the width of noise included in one horizontal period H is H/2.
If the up-down counter 23 is below, all non-inverting output terminals Q ₁ to Q _o will start from "0" at the beginning of the pulse period (when the switching terminal becomes logic 1), and the original accuracy will be It always operates with a reliable counting function and can reliably separate vertical pulses. Further, the comparator circuit 35 is set to prevent the counter circuit 36 from operating due to short pulse noise of about one clock, for example. It also has a function of accurately detecting the timing phase of the rise of the vertical pulse. The counter circuit 36 is set so that it will not output erroneous vertical pulses even when noise of 2 clocks or more and less than H/2 period is instantaneously added, and it will count the clocks to a certain extent when a rising pulse is added. The settings are such that the output is output after

According to the invention described above, it is possible to provide a vertical synchronization detection circuit that is suitable for an integrated circuit with low power consumption and can reliably separate vertical pulses with a stable phase without being affected by noise.

[Brief explanation of the drawing]

FIG. 1 is a configuration explanatory diagram of a conventional vertical synchronization detection circuit, FIGS. 2 a to d are signal waveform diagrams of various parts of the circuit in FIG. 1, and FIG. 3 is a configuration showing an embodiment of the vertical synchronization detection circuit of the present invention. The explanatory diagram, FIG. 4, is a signal waveform diagram shown to explain the operation of the circuit of FIG. 3. 22...Synchronization separation circuit, 23...Up-down counter, 24...Up-down switching terminal, 25
... Clock pulse input terminal, 26, 27 ... NAND circuit, 35 ... Comparison circuit, 36 ... Counter circuit.

Claims (1)

[Scope of Claims] 1. Synchronization separating means for separating a composite synchronizing signal from a video signal; Clock pulse generating means for generating continuous clock pulses having a plurality of pulses during at least the pulse period of the horizontal synchronizing signal; an up-down counter that counts up or down the clock pulses generated by the clock pulse generating means, and whose up or down counting operation is switched according to the polarity of the composite synchronization signal separated by the synchronization separation means; Comparing means for comparing the count value output from the down counter with a predetermined comparison value and generating a vertical synchronization detection pulse when the count value is greater than or equal to the comparison value; and the synchronization detection pulse generated by the comparison means and the clock pulse. 1. A vertical synchronization detection circuit comprising: a counter means for generating a vertical detection pulse by counting a predetermined clock pulse during the period of the synchronization detection pulse.