JPS6150430B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a vertical synchronization detection circuit that extracts a vertical synchronization pulse from a composite synchronization pulse train separated from a television signal.

A conventional circuit for detecting a vertical synchronizing pulse from a composite synchronizing pulse in a television receiver or the like is shown in FIG. That is, a composite synchronizing pulse is applied to the input terminal 11, and the applied signal is applied to the integrator circuit 12.
The voltage is applied to the voltage comparator circuit 13 via the voltage comparator circuit 13. Since the pulse width is small during the horizontal pulse or equivalent pulse period, the voltage obtained from the integrating circuit 12 cannot exceed the voltage level set in the voltage comparator circuit 13. However, when a vertical synchronizing pulse with a large pulse width as shown in FIG. 2a is applied, an output as shown in FIG. Here, the output voltage of the integration circuit 12 is compared with the voltage level set in the voltage comparison circuit 13, as shown in FIG. 2c, and there is a section in which it exceeds a threshold value. During this period, a vertical synchronizing pulse as shown in FIG.

According to the above-described conventional vertical synchronization detection means, even in today's world where integrated circuits are popular, it is still difficult to integrate them. This is because it is difficult to create a capacitor with high precision and a large capacitance within an integrated circuit, and adding a capacitor outside the integrated circuit requires an increase in the number of pins in the circuit. This is because there is a restriction.

The present invention has been made to address the above-mentioned circumstances, and an object of the present invention is to provide a vertical synchronization detection circuit that is suitable for integration into an integrated circuit, and which is unaffected by noise and obtains pulses with a stable phase. do.

Embodiments of the present invention will be described below with reference to the drawings. That is, in FIG. 3, 21 is an input terminal to which a composite video signal is applied, and is connected to a synchronization separation circuit 22. This synchronization separation circuit 22 separates synchronization signals, and the output terminal from which a composite synchronization pulse is obtained is connected to an up-down switching terminal 24 of an up-down counter 23. The up-down counter 23 has flip-flop circuits F ₁ to _{F o} provided in multiple stages. A clock pulse input terminal _Cp is set at the clock terminal of the first stage flip-flop circuit _F1 . The first connection configuration of the flip-flop circuit is
The representative explanation of the first stage and second stage is as follows. Non-inverting output terminal of flip-flop circuit _F1
Q ₁ is connected to the first input terminal of the AND circuit AG ₁ and also to the input terminal of the NAND circuit 26 . Further, the inverting output terminal ₁ of this flip-flop circuit F ₁ is connected to the first input terminal of the AND circuit DG ₁ and also to the input terminal of the NAND circuit 27 . Further, the up-down switching terminal 24 is connected to a second input terminal of the AND circuit AG ₁ , and the up-down switching terminal 24 is connected to a second input terminal of the AND circuit DG ₁ via an inverter NT. . And the said AND circuit
The output terminals of AG ₁ and DG ₁ are the first and second terminals of OR circuit OR ₁ .
connected to each input terminal. The output terminal of this OR circuit OR ₁ is a flip-flop circuit.
Connected to the clock input of _F2 . The second and third stages, and the third and fourth stages are successively connected using the same connection circuit configuration as the flip-flop circuits F ₁ and F ₂ above, and the flip-flop circuit F _o in the final stage is connected in sequence. The inverted output terminal _Qo is connected to the input terminal of the NAND circuit 26, and the inverted output terminal is connected to the NAND circuit 2.
It is connected to the input terminal of 7. Further, the up/down switching terminal 24 is connected to the input terminal of the NAND circuit 26, and the inverter
It is connected to the input end of the NAND circuit 27 via NT.

The output logic value of the NAND circuit 26 is set by each logic of the non-inverting output terminals Q ₁ -Q _o of the flip-flop circuits F ₁ -F _o and the up/down switching terminal 24. The output logic value is set by each logic of the inverting output terminals ₁ to ₀ of the circuits F ₁ to F _o and the inverter NT. the NAND circuit 26,
The output terminals of 27 are connected to AND circuits 29 and 30, respectively.
are connected to each first input terminal of the. The second input terminal of the AND circuit 29 is connected to the output terminal of the synchronous separation circuit 22. The output terminal of the inverter NT is connected to the second input terminal of the AND circuit 30, so that the output of the synchronous separation circuit 22 is inverted and applied thereto.

Furthermore, output terminals of first and second clock pulse generation circuits 31 and 32 are connected to the third input terminals of the AND circuits 29 and 30, respectively.
The output terminals of the AND circuits 29 and 30 are connected to the first and second input terminals of an OR circuit 28, and the output terminal of the OR circuit 28 is connected to the clock pulse input terminal 25 of the up-down counter 23. There is.

The non-inverting output terminals Q ₁ -Q _o of the flip-flop circuits F ₁ -F _o are also connected in parallel to one input terminal of a comparator circuit 35. The other input terminal of this comparison circuit 35 is set with predetermined data (number) to be compared. This comparator circuit 35 derives a rising pulse when the output data state from the up-down counter 23 becomes larger than the set data, and its output terminal is connected to a counter circuit 36. This vertical pulse generation counter circuit 36
When the output pulse from the comparator circuit 35 continues for a certain period of time, it outputs a vertical synchronizing pulse to the output terminal 37. In order to obtain the generation timing, the clock pulse generating circuit is connected to the clock input terminal. The output end of 31 is also connected.

The vertical synchronization detection circuit according to the present invention is constructed as described above.Next, the functions and operations of each part will be explained with reference to the waveform diagram of FIG. 4. first,
The up-down counter 23 is switched between up-counting and down-counting functions by a composite synchronization pulse applied to its up-down switching terminal 24. In other words, the horizontal sync pulse interval (approximately
5.1 μs), an equivalent pulse period (approximately 2.5 μs), and a vertical synchronization pulse period (approximately 29.3 μs) (high level), it performs an up-count operation, and in other periods (low level), it performs a down-count operation. This means that when a pulse is applied to the switching terminal 24 and the logic is 1, the non-inverting output terminals Q ₁ to Q _o
AND circuits connected to each side AG ₁ ~
When the gate of AG _o-1 is opened and counting up, and the switching terminal 24 is logic 0, the inverted output terminal ₁ ~ _o
AND circuits connected to each side DG ₁ ~
By counting down by opening the gate of DG _o-1 via inverter NT.

When the synchronization pulse is logic 1 and up count,
The AND circuit 29 is on and the AND circuit 30 is off. When all the logic inputs to the NAND circuit 26 become "1", the output logic of the NAND circuit 26 becomes "0" and the gate of the AND circuit 28 is closed. Therefore, the clock pulse from the clock pulse generating circuit 31 is no longer applied. Therefore, up-down counter 2 in this case
The output state of No. 3 is maintained as it is. Further, when the synchronization pulse becomes 0, the AND circuit 29 is turned off and the AND circuit 30 is turned on. Therefore, the output of the clock pulse generation circuit 32 is applied to the up-down counter. During this down count, when all the logic inputs to the NAND circuit 26 become "0" as the down count progresses, all the logic inputs to the NAND circuit 27 become "1", and the output of this NAND circuit 27 is It becomes logic 0 and turns off the gate circuit 30. Therefore, the counting operation of the up-down counter stops. Therefore, the loop of the NAND circuit 26, the AND circuit 29, the OR circuit 28, and the period separation circuit 2
The output logic of 2 forms a counter overflow prevention circuit, and the loop of the NAND circuit 27, AND circuit 30, OR circuit 28, and the output logic of the synchronous separation circuit 22 form a counter underflow prevention circuit. are doing.

Next, the operation during the horizontal synchronizing pulse period (approximately 5 μs) will be explained. In this case, the up/down switching terminal 24 is at the logic of synchronous pulse "1". Now, assuming that the output frequency of the clock pulse generation circuit 31 is m, the up count number is m×T _p (T _p =horizontal periodic pulse period approximately 5 μs). This counted binary code is applied to a comparison circuit 35. Next, the switching terminal 24 becomes logic 0, and the gates of the AND circuits DG ₁ to _{DG o-1} provided on the inverting output terminal side are opened. This provides a down count function. Further, in this case, the AND circuit 29 is turned off and the AND circuit 30 is turned on, depending on the output logic of the synchronization separation circuit 22. Therefore, the output of the clock pulse generation circuit 32 is now applied to the up-down counter 23. In this case, the frequency of the clock pulse generating circuit 32 is set to n, for example. By the clock pulse of this frequency, the up-down counter counts m×T _p (the amount counted by the up-count). As this count progresses and all input terminals of the NAND circuit 26 become 0 and all output terminals of the NAND circuit 27 become 1, the underflow prevention function is activated. When the horizontal period passes and the next horizontal sync pulse comes,
The above operation will be repeated. Therefore, the period of up and down counting of the up-down counter 23 is as shown in period T1 in FIG _.
m/nT _p ) period. Here, the output (rising pulse) of the comparator circuit 35 is set to occur from the second clock, and the vertical pulse generation counter circuit 36 counts the clock pulses for a predetermined period after the rising pulse is added. It is arranged to deliver a vertical pulse to the output end 37. This vertical pulse generation counter circuit 3
6 means that the clock pulse lasts for more than one horizontal period (approximately 64
(μs = 64 clock pulses) It is set to generate a vertical pulse when counting is performed.
Therefore, no vertical pulse is generated at the number of clocks when a horizontal synchronizing pulse is added.

Next, the operation will be explained in terms of equivalent pulses. The pulse width of the equivalent pulse is approximately 2.5 μs,
The period during which the up-down counter 23 is operating is shorter than when the above-mentioned horizontal synchronizing pulse arrives, and naturally the vertical pulse generating circuit 36 does not generate a vertical pulse.

Next, the operation in the vertical synchronization pulse section will be explained. The pulse width of the vertical synchronization pulse is approximately 29.3μs
There is a gap of about 2.5 μs, and this occurs repeatedly six times (for three horizontal line periods). In the vertical synchronization pulse part, the up-down counter 23
counts up a count corresponding to approximately 29.3 μs (for example, clock pulse generation circuit 3
(If the clock pulse of 1 is 1 μs, the number of counts is about 29) Then there is a gap of about 2.5 μs, so the clock from the clock pulse generation circuit 32 counts down during this 2.5 μs period. If the ratio of m and n is selected so that the next vertical synchronizing pulse arrives before the number becomes 0, the count-up number will be further increased and this operation will be repeated six times. Therefore, the operating period of the up-down counter 23 is sufficiently longer than the time when the above-mentioned horizontal synchronizing pulse arrives. Therefore, a vertical pulse can be obtained from the vertical pulse generation counter circuit 36.

As described above, according to the circuit of the present invention, the frequency of the clock pulse is different between the up-count operation and the down-count operation of the up-down counter. In this case, as shown in FIG. 4, m:n=1:
If set to 2, the ratio of the count period will be 2:1. For example, if noise etc. is mixed into the synchronization signal, and the integral value of the noise period is not more than 2/3 of the total period, this circuit will ignore the noise. Not affected by For example, as shown in FIG. 4, even if the noise N corresponding to the (2/3) H period is mixed in, the output pulse from the comparator circuit 35 is counted up and down, so the output pulse from the comparator circuit 35 is less than one horizontal period. 36
No vertical pulse is output from. However, if the vertical synchronization pulse is missing due to noise, the permissible limit is up to 1/3 of the period, so the ratio of m and n should be adjusted in consideration of the characteristics of the synchronization separation circuit 22. It is preferable to make it possible. In other words, if the bias of the synchronization separation circuit 22 is set deeply and positive polarity noise becomes more likely to appear, m>n
is less affected by noise. Furthermore, if the bias is set shallowly and the negative polarity component is likely to be lost, it is better to set m<n. Note that in this invention, it is not necessary to create two clock pulse generation circuits, as long as one clock pulse generation circuit and a frequency dividing circuit are used to generate clock pulses of two different frequencies, the same operation as in the above embodiment can be achieved. Of course, the same effect can be obtained even if a monostable multivibrator circuit or an analog integrating circuit is used instead of the counter circuit 36 to detect pulses for a certain period of time.

As described above, according to the present invention, it is possible to provide a vertical synchronization detection circuit that is suitable for integrated circuits with low power consumption and can reliably separate vertical pulses with a stable phase without being affected by noise.

[Brief explanation of the drawing]

FIG. 1 is a configuration explanatory diagram of a conventional vertical synchronization detection circuit, FIGS. 2 a to d are signal waveform diagrams of various parts of the circuit in FIG. 1, and FIG. 3 is a configuration showing an embodiment of the vertical synchronization detection circuit of the present invention. The explanatory diagram, FIG. 4, is a signal wave diagram shown to explain the operation of the circuit of FIG. 3. 22...Synchronization separation circuit, 23...Up-down counter, 24...Up-down switching terminal, 25
... Clock pulse input terminal, 26, 27 ... NAND circuit, 28 ... OR circuit, 29, 30 ... AND circuit, 31, 32 ... Clock pulse generation circuit.

Claims (1)

[Scope of Claims] 1. A synchronization separating means for separating a composite synchronization signal from a video signal; , a clock pulse generating means for deriving a second clock pulse, and selecting the first clock pulse with one polarity of the composite synchronization signal separated by the synchronization separation means among the clock pulses derived from the clock pulse generation means, and selecting the first clock pulse with the other polarity. a clock pulse selection means for selecting a second clock pulse with the polarity of the clock pulse selection means; and a clock pulse selection means for counting up or down the clock pulse selected and output by the clock pulse selection means, the up or down counting operation depending on the polarity of the composite synchronization signal. and a comparison means for comparing the count value output from the up-down counter with a predetermined comparison value and generating a vertical synchronization detection pulse when the count value is greater than or equal to the comparison value. A vertical synchronization detection circuit characterized by: