JPS5556768A - Vertical synchronism detector circuit - Google Patents

Vertical synchronism detector circuit

Info

Publication number
JPS5556768A
JPS5556768A JP13034678A JP13034678A JPS5556768A JP S5556768 A JPS5556768 A JP S5556768A JP 13034678 A JP13034678 A JP 13034678A JP 13034678 A JP13034678 A JP 13034678A JP S5556768 A JPS5556768 A JP S5556768A
Authority
JP
Japan
Prior art keywords
counter
pulse
counting
synchronous
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13034678A
Other languages
Japanese (ja)
Other versions
JPS6150430B2 (en
Inventor
Hiroo Kitazawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP13034678A priority Critical patent/JPS5556768A/en
Publication of JPS5556768A publication Critical patent/JPS5556768A/en
Publication of JPS6150430B2 publication Critical patent/JPS6150430B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Synchronizing For Television (AREA)

Abstract

PURPOSE: To obtain a vertical synchronism detector circuit which is suited for formation into the integrated circuit and can obtain the pulse of the steady phase.
CONSTITUTION: The composite synchronous pulse isolated by synchronous isolator circuit 22 is applied to up-down counter 23. And counter 23 is switched to the up-counting when the synchronous pulse exists and to the down-counting when no synchronous pulse exists. Up-counting clock pulse generator circuit 31 is provided along with down-counting clock pulse generator circuit 32, and the both circuits generate the clock pulses of different frequencies to each other. Then the output of counter 23 is supplied to comparator 35 to be compared with the data determined previously. Comparator 35 delivers the rise pulse when the output given from counter 23 becomes larger than the set data. Thus counter 36 is driven to lead out the vertical synchronous pulse to output terminal 37.
COPYRIGHT: (C)1980,JPO&Japio
JP13034678A 1978-10-23 1978-10-23 Vertical synchronism detector circuit Granted JPS5556768A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13034678A JPS5556768A (en) 1978-10-23 1978-10-23 Vertical synchronism detector circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13034678A JPS5556768A (en) 1978-10-23 1978-10-23 Vertical synchronism detector circuit

Publications (2)

Publication Number Publication Date
JPS5556768A true JPS5556768A (en) 1980-04-25
JPS6150430B2 JPS6150430B2 (en) 1986-11-04

Family

ID=15032185

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13034678A Granted JPS5556768A (en) 1978-10-23 1978-10-23 Vertical synchronism detector circuit

Country Status (1)

Country Link
JP (1) JPS5556768A (en)

Also Published As

Publication number Publication date
JPS6150430B2 (en) 1986-11-04

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