JPS5588472A - Reset pulse forming circuit - Google Patents

Abstract

PURPOSE: To always ensure the resetting for the vertical synchronism in the same timing regardless of the types of the external synchronous signals by providing the forming circuit of the pulse signal synchronized with the external composite synchronous signal to obtain the horizontal and vertical synchronous pulse signals.

CONSTITUTION: The reset pulse forming circuit consists of forming circuit 10 for the pulse signal synchronized with the external composite synchronous signal pulse pulse forming circuit 20 which forms the reset pulse via the horizontal and vertical synchronous pulse signals obtained from circuit 10. PLL1 of circuit 10 gives the phase comparison between the output obtained by giving the 1/n division to the frequency of VCO5 through counter 6 and horizontal synchronous pulse signal SH via phase comparator 7, and this comparison output is changed into the control voltage of VCO through LPF8. Forming circuit 2 consists of counter 11 and inhibit circuit 12 and forms horizontal synchronous pulse signal SH. Forming circuit 3 comprises counter 15 and FF16 to form vertical synchronous pulse signal SV. The reset pulse is formed at circuit 20 and based on pulses SH and SV, and the timing is adjusted for the field pulse synchronized with the external synchronous input through timing adjusting circuit. Thus the accurate reset pulse is obtained.

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