JPS6159034B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a vertical synchronization reset pulse forming circuit for synchronization signal generators of the PAL system and the so-called PAL-M system.

In order to synchronize the vertical synchronization signal obtained from the synchronization signal generator with the external vertical synchronization signal, the vertical synchronization signal forming circuit (frequency dividing circuit) is reset (V-reset) based on the external synchronization signal (reference signal). . In addition, in the PAL system, the phase of the R-Y subcarrier is inverted line by line, and it is necessary to generate a signal to control this inversion in synchronization with an external synchronization signal. for
It is necessary to create a reset signal that occurs on a specific field of 4V. In this case PAL-
In the M system, the configuration of the external synchronization signal serving as the reference signal is not single, but there are multiple types, and the configurations can be roughly divided into the following two types.

There is a so-called VBS signal as the first external synchronization signal. This is a composite signal that is the same as a normal color video signal composed of a video signal, a burst signal, and a composite synchronization signal. To form a reset pulse from this composite signal, for example, a composite synchronization signal and a burst flag pulse formed from the composite synchronization signal are used.

Note that the so-called BS signal composed of a burst signal and a composite synchronization signal has no essential difference from the first external synchronization signal.

The second external synchronization signal may be a composite signal consisting of a composite synchronization signal, a line signal (or PAL-pulse), and a color subcarrier signal. In this case as well, a reset pulse is formed based on this composite synchronization signal and line signal.

The reset pulse forming circuit must be constructed so that a reset pulse can always be obtained in a predetermined field at the same timing (same phase) regardless of which of the first and second external synchronization signals is input.

In other words, if the field in which the reset pulse is obtained differs depending on the type of external synchronization signal, or if the timing in which the reset pulse is obtained differs even in the same field, the synchronization signal generation regulated by this reset pulse may be affected. This is because the phase of the PAL-pulse or line signal from the device cannot always be maintained in a fixed phase relationship with respect to the phase of the external synchronization signal.

Therefore, the present invention proposes a reset pulse forming circuit that can always obtain a reset pulse in the same field at the same timing, regardless of the type of external synchronization signal. The present invention particularly targets synchronization signal generators of the PAL system and the PAL-M system.

Next, an example of the present invention will be explained with reference to FIG. 1. This embodiment is a PAL-M reset pulse forming circuit, and the external synchronization signals include the first and second external synchronization signals. Consider the synchronization signal.

As shown in the figure, the reset pulse forming circuit according to the present invention includes a pulse signal forming circuit 10 synchronized with an external composite synchronizing signal, and a reset pulse forming circuit 10 for forming a reset pulse from the horizontal period and vertical period pulse signals obtained from the pulse signal forming circuit 10. It is composed of a pulse forming circuit 20. A signal based on an external synchronization signal is supplied to the terminals 30a to 30c. That is, terminal 3
0a is supplied with an external composite synchronization signal COP {Fig. 2 _A1 (first field) to _A4 (fourth field)}, and a burst flag pulse BF is supplied to terminal 30b.
(C ₁ to C ₄ in the figure) are supplied, and a line signal ALT (B ₁ to _{B 4} in the figure) is supplied to the terminal 30c.

The burst flag pulse BF is formed, for example, based on the external composite synchronization signal COP and the burst signal as described above.

The pulse signal forming circuit 10 is configured using a plurality of frequency dividing counters. This formation circuit 10
, 1 is a clock pulse P _C forming circuit;
2 is a circuit for forming a horizontal period pulse signal S _H having a predetermined pulse width based on the external composite synchronization signal COP, and 3 is a circuit for forming a vertical period pulse signal S _V from the external composite synchronization signal. This is the circuit.

The clock pulse P _C forming circuit 1 is configured as a PLL. 5 is a VCO whose oscillation frequency is nf _H
(n≧4, f _H is the horizontal synchronization frequency), which is counted down to 1/n by the frequency division counter 6, and its output is phase compared with the horizontal period pulse signal S _H as described later. The phase comparison output is supplied to the VCO 5 as its control voltage through the low-pass filter 8, whereby the clock pulse P is locked to the phase of the horizontal synchronization signal P _H of the external composite synchronization signal COP. _C
is formed.

As shown in the figure, the circuit 2 for forming the horizontally periodic pulse signal S _H is composed of a counter 11 and an inhibit circuit 12 provided on the reset terminal R side of the counter 11.
COP is supplied. Therefore, this counter 11
is reset by the external composite synchronization signal COP, but if this synchronization signal COP itself is reset, the counter 11 will obtain a horizontal period pulse signal S _H when the equalization pulse or vertical synchronization pulse P _V is input. Therefore, when these pulses are input, it must be devised so that it does not respond to pulses every 1/2 horizontal period, but only responds to pulses every 1 horizontal period.

For this purpose, first, the pulse width W ₁ of the first pulse signal S _H obtained from the counter 11 is selected to be greater than or equal to 1/2 horizontal period and less than or equal to 1 horizontal period. Therefore, the counter 11 is selected so that the counting state is stopped and the counter output is inverted when the count number x after the counting state is reset satisfies the expression (2).

1/2<x/n<1 ...(1) ∴n<2x<2n ...(2) In addition, if the pulse width W ₁ is selected for the 3/4 horizontal period, the PLL system of the formation circuit 1 Therefore, the first forming circuit 2 will not malfunction even due to jitter that occurs until the phase of the clock pulse P _C is locked.

Then, counter 11 is added every 1/2 horizontal period.
In order to prevent the counter from being reset, the counter output and the inhibit output of the composite synchronization signal COP are supplied to the counter 11 as a reset pulse.
The third example describes the operation when the composite synchronization signal COP is input.
This will be explained with reference to the figures. However, in the same figure, the signals A ₁ , B ₁ ... H ₁ with the subscript "1" are signals related to odd fields, and the signals with the subscript "2"
The signals A ₂ , B ₂ . . . H ₂ are signals related to even fields. And symbols without subscripts D, I, J,
K is a signal common to both fields.

In an odd field, when the horizontal synchronizing pulse P _H is input to the counter 11, the counter 11 is reset and starts counting, and x
When the counter output is inverted, a pulse signal S _HO having a pulse width W ₁ corresponding to the count number x is obtained. In the equalization pulse section, the counter 11 is reset with the first pulse, but in the next equalization pulse in the 1/2 horizontal period,
Since the counter output is "1", the inhibit output does not change and is not reset by this equalization pulse. However, since the counter output is "0" at the third equalization pulse (corresponding to the first horizontal period from the first equalization pulse), when this pulse is input, a reset pulse is obtained and the counter 11 is reset. The operation is the same in the period of the vertical synchronization pulse _Pv .

In this way, a pulse signal S _HO (FIG. 3 B ₁ ) synchronized with the horizontal synchronizing pulse P _H included in the composite synchronizing signal COP(O) is formed. In an even field, a pulse signal _SHE shifted by 1/2 horizontal period is obtained as shown in _B2 of the same figure.

As shown in the figure, the circuit 3 for forming the vertical period pulse signal S _V is composed of a counter 15 and a D-type flip-flop circuit 16, and the counter 15 in this case is reset by all the synchronization signals included in the composite synchronization signal COP. be done as it is done. Pulses P _CK of C ₁ and C ₂ in FIG. 3 obtained from the counter 15
The pulse width W ₂ of (P _CKO , P _CKE ) is arbitrary as long as it is less than 1/2 horizontal period and more than the pulse width of the synchronizing signal.

The pulse _PCK is supplied to the flip-flop circuit 16 as a clock pulse, and the D terminal is supplied with a composite synchronization signal COP. Therefore, from this flip-flop circuit 16, a pulse signal S _V with a vertical period as shown in FIG. 2D is obtained regardless of whether it is an odd field or an even field. This pulse signal S _V is obtained in synchronization with the vertical synchronization pulse P _V included in the composite synchronization signal COP of A ₁ and A ₂ in the same figure.

The pulse forming circuit 20 forms a target reset pulse P _R based on the horizontal period pulse signal S _H and the vertical period pulse signal S _V. First, in order to form first and second shift pulses P ₆ and P ₇ having different shift amounts and pulse widths, a 7-bit shift register 21 consisting of a D-type flip-flop circuit is used.
A pulse signal S _V is supplied to the D terminal of the circuit, and an external composite synchronization signal COP is supplied as a clock pulse.

In this example, the first shift pulse P ₇ shifted by 7 bits (F ₁ , F ₂ in the same figure) and the second shift pulse P ₆ shifted by 6 bits (E ₁ , E ₂ in the same figure) are output, and the first The shift pulse P ₇ is used when the first external synchronization signal is supplied, and the second shift pulse P ₆ is used when the second external synchronization signal is supplied. The case will be explained starting from the case where the first external synchronization signal is supplied.

The first shift pulse ₇ (G ₁ , G ₂ in the same figure) inverted by the inverter 22 is a burst flag pulse.
It is supplied to the AND circuit 23 along with BF, but the second
The burst flag pulse BF ₂ in the field is shown in the same figure.
H ₁ , the burst flag pulse BF ₄ in the fourth field is H ₂ in the same figure, and the first shift pulse _7E in the even field is G ₂ in the same figure. Only in the case of a field, the AND output P _BF (same figure) is obtained. That is, this AND output _PBF becomes a field pulse corresponding to a specific field.

24 is a timing adjustment circuit, which is composed of two-stage flip-flop circuits 25A and 25B.
When external synchronization signal is input, switch SW
is switched as shown in the figure, so the field pulse _PBF is connected to the RS type flip-flop circuit 25A.
This is supplied as a reset pulse. A horizontally periodic pulse signal S _HE is supplied as the set pulse, so that an inverted output ₁ shown in J in the figure is obtained, which is supplied as data to the D-type flip-flop circuit 25B at the subsequent stage.

If the horizontal period pulse signal S _HE is used as a clock pulse for the flip-flop circuit 25B, a pulse P _R as shown by K in the figure can be obtained over a period of 1H immediately after the inverted output ₁ is obtained.
This pulse _PR is used as a reset pulse.

Next, the formation of a reset pulse when a second external synchronization signal is input instead of the first external synchronization signal will be explained with reference to FIG. At this time, the second shift pulse P ₆ is used, and this and the horizontal period pulse signal S _H are supplied to the counter 27. This counter 27 is a 3-bit counter, and the output of the highest digit ( ²² digits) is used as the counter output Pa.

The first shift pulse P ₆₀ obtained in the odd field is in a counting state for a period T _O (E ₁ in Fig. 4), but since the pulse signal S _HO input during this period T _O is 3 pulses, there are 3 pulses. The eye counter output is 0 (G ₁ in the figure). On the other hand, in the even field, the shift pulse P _E is input, and at this time, the pulse signal S _HE is counted four times during the period T _E , so the counter output of the fourth pulse becomes "1", and in the same figure G ₂ counter output Pa is obtained.

On the other hand, the line signal ALT ₂ in the second field is _H1 in the same figure, and the line signal in the fourth field is
Since ALT ₄ is H ₂ in the figure, if this line signal ALT and the counter output Pa are ANDed in the AND circuit 28, the AND output shown in I in the figure is obtained only in the case of the fourth field, that is, the field pulse P _AL
T is obtained. Since this field pulse _PALT is supplied to the flip-flop circuit 24 through the switch SW, the inverted output ₁ shown in J in the figure is obtained as in the case described above, so that the pulse K in the figure, that is, the reset pulse _P'R , is obtained. That's what you get.

Here, both the reset pulse P _R formed when the first external synchronization signal is input, and the reset pulse P' _R formed when the second external synchronization signal is input, are in the fourth field. Moreover, since they are obtained at the same timing, the V-reset for the synchronizing signal generator can always be reset at the same timing, regardless of the type of external synchronizing signal.

That is, although the field pulse P _BF when the first external synchronization signal is used and the field pulse P _ALT when the second external synchronization signal is obtained are different in timing, the timing adjustment circuit 24 adjusts the timing between the two. The timings of the reset pulses P _{R and} P' R are adjusted so that the reset pulses P R and P' _R are always obtained at the same timing.

As explained above, according to the present invention, regardless of the type of external synchronization signal, the reset pulses P _R ,
Since both _P'R 's are obtained in the fourth field and at the same timing, the vertical synchronization can always be reset at the same timing regardless of the type of external synchronization signal.

In addition, in the above-mentioned embodiment, this invention is applied to PAL-
This is a case in which the present invention is applied to an M system reset pulse forming circuit, but it can also be applied to an NTSC system. In this case, it is sufficient to switch the switch SW to the 2 side and set the input level of the terminal 30c to a high level.

[Brief explanation of the drawing]

FIG. 1 is a system diagram showing an example of the present invention, and FIGS. 2 to 4 are waveform diagrams for explaining its operation. 10 is a forming circuit for pulse signals S _H and S _V ; 20 is a pulse forming circuit for reset pulses P _R and P'_R;
COP is an external composite synchronization signal, BF is a burst flag pulse, ALT is a line signal, 24 is a timing adjustment circuit, 21 is a shift register, P _BF , P _ALT
is the field pulse.

Claims (1)

[Claims] 1 A horizontal period pulse signal and a vertical period pulse signal are formed from the external composite synchronization signal, first and second shift pulses having different shift amounts and pulse widths are formed from these pulse signals, and the second shift pulse A pulse corresponding to an odd field or an even field is formed from the horizontal period pulse signal, and this pulse and an external line signal or external
A field pulse corresponding to a specific field is formed based on the PAL pulse, and a field pulse corresponding to the same field as the above field is formed based on the first shift pulse and the external burst flag pulse. A reset pulse forming circuit in which any of the pulses is supplied to a timing adjustment circuit so that a reset pulse is formed in the specific field at the same timing regardless of the type of external synchronization signal.