JPH01228325A - Digital phase locked loop circuit - Google Patents

Abstract

PURPOSE:To reduce the phase change step for phase correction without changing a fixed frequency signal by inverting the phase of the fixed frequency signal at the time of phase advance or phase delay to set the phase change step for phase correction to a half period of the fixed frequency signal. CONSTITUTION:The phase of an input signal and that of an output signal are compared with each other by a phase comparator 10, and a phase advance output or a phase delay output is sent to a control circuit 18 as the result. The fixed frequency signal is sent to a phase inverting circuit 14 through a buffer 26 and an inverter buffer 27, and its phase is selected by a phase inverting circuit 14. The control circuit 18 sets a frequency division ratio in accordance with phase advance or phase delay and sends it to a frequency divider 11. Simultaneously, a control signal is sent to the phase inverting circuit 14 and the phase of the fixed frequency signal sent to the frequency divider 11 is inverted by the phase inverting circuit 14. The fixed frequency taken into the frequency divider 11 is advanced or delayed by a half period, and the frequency division ratio or the fixed frequency signal in the frequency divider 11 is raised twice apparently.

Description

[Detailed Description of the Invention] Overview Regarding a digital phase-locked loop circuit that digitally corrects the phase, the purpose is to reduce the phase change step during phase correction without changing the fixed frequency signal. In a digital phase-locked loop circuit that compares the phases of output signals using a phase comparator and corrects them using a frequency divider if the phases differ between the two, the phase of the fixed frequency signal that is the operating clock of the frequency divider is A phase inversion circuit that inverts the
A control circuit that sends a control signal to a frequency divider and a phase inversion circuit according to a phase lead or a phase lag is provided, and a phase change step for phase correction is performed by inverting the phase of a fixed frequency signal when a phase lead or a phase lag occurs. 1/ of fixed frequency signal
It is configured to have two cycles.

INDUSTRIAL APPLICATION FIELD The present invention relates to a digital phase-locked loop circuit that digitally corrects the phase.

Phase-locked loop circuits are widely used in fields such as television synchronization signal generation circuits, color processing circuits, satellite broadcasting audio demodulation, and FM detection. Additionally, phase-locked loop circuits can be roughly divided into analog types and digital types, which have a digitalized signal processing method.Digital phase-locked loop circuits have improved operational stability and reliability compared to analog types. It is mainly used in the space communications and digital communications fields.

Digital phase-locked loop circuits synchronize signals by inserting or deleting pulses in the output of a fixed frequency oscillator to change the frequency, or by changing the division ratio of a frequency divider. As described above, since phase correction is performed digitally, there is a demand for a digital phase-locked loop circuit that can efficiently reduce the phase change step during phase correction, depending on the use of the phase-locked loop.

FIG. 4 shows a block diagram of a conventional digital phase-locked loop circuit.

10 is a phase comparator, 19 is a control circuit, and 11 is a frequency divider (digital VCO).The frequency f of a fixed frequency signal, which is the operating clock of the frequency divider 11.
Nf,o (N is an integer of 2 or more, f is the frequency of the input signal).

n The frequency f of the input signal, and the frequency f of the output signal. .

n 1 is compared by the phase comparator 10 for each period, and the comparison result is sent from the phase comparator 10 to the control circuit 19 as a phase lead output or a phase lag output. The control circuit 19 transmits the control signal to the frequency divider 11 according to the phase lead output or the phase delay output from the phase comparator 10.
Send to. Then, the frequency divider 11 digitally corrects the phase of the signal to be output based on instructions from the control signal. The corrected output signal is sent to the phase comparator 1 again.
By repeating this series of operations while the phase is compared with the input signal at 0, synchronization between the input signal and the output signal is established, and the frequencies f and f become equal.

+n out Also, Fig. 5 is a configuration diagram of a conventional control circuit and frequency divider, and Fig. 6
The figure shows a timing chart of a conventional example, and its configuration and operation will be explained below.

The control circuit 19 is composed of a counting circuit 20 and a frequency dividing ratio control circuit 21, and the frequency divider 11 is composed of a frequency dividing circuit 12 and a frequency dividing circuit 1.
It consists of 3. The counting circuit 20 is an OR circuit 31
．． 32. It is composed of a k-stage shift register 28, 30 and an m-stage shift register 29, and counts the phase lead output or phase delay output signal outputted by the phase comparator 10, and when the number of times reaches a predetermined number, It is sent to the frequency division ratio control circuit 21 as a phase lead signal or a phase lag signal. The frequency division ratio control circuit 21 sets a frequency division ratio according to the phase lead signal or the phase lag signal, and sends the set frequency division ratio to the frequency division circuit 12 as a control signal. The frequency dividing circuit 12 is constituted by a counter equipped with a preset terminal, and when the frequency division ratio is N, it counts the input clock by N and simultaneously outputs an N divided output (see point a in Fig. 6). ).

The divide-by-2 circuit 13 is composed of a flip-flop. Note that the frequency divider circuit 12.2 and the frequency divider circuit 13 are designed to operate at the rising edge of the operation clock.

The phase lead output from the phase comparator 10 is sent to the k-stage shift register 28, and is also sent to the m-stage shift register 28 via the OR circuit 31.
It is sent to the stage shift register 29. The phase-delayed output is sent to the second stage shift register 30, and is also sent to the OR circuit 3.
1 to the m-stage shift register 29. Here, the value of 1m in the k-stage shift register 28.30 and the m-stage shift register 29 is an integer having a relationship of -2 where k<m≦2. Thereby, when a phase lead or a phase lag occurs a few times, it is sent to the frequency division ratio control circuit 21 as a phase lead signal or a phase lag signal. At the same time, a register clear signal is generated from the OR circuit 32, and the k-stage shift register 28, 30 and the m-stage shift register 29 are cleared. Furthermore, if the sum of the phase advance and phase lag reaches m times before the phase advance or phase lag occurs several times, the OR circuit 32
A register clear signal is generated, and the k-stage shift registers 28, 30, . The m-stage shift register 29 is cleared.

When neither a phase lead signal nor a phase lag signal is generated, the division ratio υJl! 1 circuit 21 sends a control signal to the frequency dividing circuit 12 side to divide the frequency fC of the fixed frequency signal by 2N. As a result, the frequency divider circuit 12 operates at the frequency of the fixed frequency signal. The frequency of the signal is divided by N, and this N-divided signal is further divided by two in a frequency divider circuit 13 to produce an output signal. The 2 frequency divider circuit 13 sets the duty ratio of the output signal fc to 5.
It is set to 0%.

When the phase advance signal is input to the frequency division ratio control circuit 21,
The frequency division ratio control circuit 21 sends 2(N+1) to the frequency division circuit 12 side.
By sending the control signal so as to divide the frequency, the phase of the output signal is delayed by 2π/N (rad) (6th
(See figure, point b). In addition, in the case of a phase delayed signal, 2(N-1
), the phase of the output signal advances by 2 yr/N (rad) (6th
(See figure, point 0).

In this way, when a phase lead signal or a phase delay signal is input to the frequency division ratio control circuit 21, the output signal is 2π/N
(rad) phase operation is performed, and the phase change step during the phase correction is one period of the fixed frequency signal.

Problems to be Solved by the Invention However, in the conventional digital phase-locked loop circuit as described above, the phase change step during phase correction is 2π/N with respect to the output signal. Therefore, in order to further reduce the phase change step, it is necessary to further increase the frequency division ratio N of the frequency divider circuit, but the frequency f of the fixed frequency signal is f02Nf, and the frequency division ratio N If you increase , the frequency f of the fixed frequency signal. frequency, and a fixed frequency signal generator with a significantly higher frequency is required. Alternatively, the operating speed limit of elements such as counters used in the frequency dividing circuit may be exceeded. As described above, there is a problem in that there is a physical limit to decreasing the phase change step by increasing the frequency division ratio N.

The present invention has been made in view of these points, and an object of the present invention is to provide a digital phase-locked loop circuit that reduces the phase change step during phase correction without changing the fixed frequency signal. be.

Means to solve problems FIG. 1 shows a block diagram of the principle of the present invention.

In a digital phase-locked loop circuit that compares the phases of an input signal and an output signal using a phase comparator 10, and corrects the phase difference between the two using a frequency divider 11,
A phase inversion circuit 14 that inverts the phase of a fixed frequency signal that is the operating clock of the frequency divider 11, and a control circuit 18 that sends a control signal to the frequency divider 11 and the phase inversion circuit 14 according to phase lead or phase lag. will be established.

With this configuration, the phase of the fixed frequency signal is inverted when the phase is advanced or delayed, so that the phase change step of the phase correction becomes 1/2 period of the fixed frequency signal.

The phases of the input signal and the output signal are compared in the phase comparator 10, and as a result, a phase lead output or a phase lag output is sent to the control circuit 18. Fixed frequency signal is buffer 26, inverter buffer? Phase inversion circuit 1 via 27
4, and its phase is selected by the phase inversion circuit 14. Then, the control circuit 18 sets a frequency division ratio according to the phase lead or phase lag, and sends this to the frequency divider 11. At the same time, a control signal is also sent to the phase inversion circuit 14, so that the phase inversion circuit 14 inverts the phase of the fixed frequency signal sent to the frequency divider 11.

The fixed frequency signal taken in by the frequency divider 11 is advanced or delayed by 1/2 period, and the appearance is the same as when the frequency division ratio in the frequency divider 11 or the fixed frequency signal is doubled.

Embodiments Hereinafter, the digital phase locked loop circuit of the present invention will be explained in detail based on embodiments shown in the drawings.

FIG. 2 shows an embodiment of a digital phase-locked loop circuit according to the present invention.

In the description of this embodiment, the same components as in FIGS. 4 and 5 will be described with the same reference numerals.

10 is a phase comparator, 11 is a frequency divider, consisting of a frequency dividing circuit 12 and a frequency dividing circuit 13, and 14 is a phase inverting circuit.
It is composed of D circuits 15 and 16 and an OR circuit 17. 18 is a control circuit, which includes a counting circuit 20 and a frequency division ratio control circuit 2.
1. Exclusive OR circuit (hereinafter referred to as EX-OR circuit) 2
2, an AND circuit 23, and a JK flip 70 tube 24. 25 is a fixed frequency oscillator that transmits a fixed frequency signal that is the operating clock of the frequency divider 11;
6 is a buffer, and 27 is an inverter buffer.

The phase comparator 10 compares the phases of the input signal and the output signal,
The counting circuit 20 counts the number of phase advances or phase lags, and when it reaches a predetermined number, sends a phase advance signal or a phase lag signal to the frequency division ratio control circuit 21 and the EX-OR circuit 22. The frequency division ratio control circuit 21 sets a frequency division ratio according to the phase lead signal or the phase lag signal, and the JK flip-flop 24 outputs a control signal for inverting the phase of the clock signal output from the phase inversion circuit 14. Sending out. The frequency division circuit 12 is constituted by a counter having a preset terminal, and a control signal from the frequency division ratio control circuit 21 is inputted to this preset terminal so that the frequency division ratio can be varied. Furthermore, when the input clock is counted by the number of frequency division ratios, a frequency-divided output pulse is output. The divide-by-2 circuit 13 is constituted by a Noritub block circuit.

FIG. 3 shows a timing chart according to the embodiment of FIG. 2, and the operation of the embodiment of FIG. 2 will be described below with reference to the timing chart of FIG. 3.

The frequency divider circuit 12.2, the frequency divider circuit 13, and the JK flip-flop 24 are designed to operate at the rising edge of the clock.

Assuming that the output of the JK flip-flop 24 is in the state of Q-1 (low level) and Q=H (high level), the operating clock of the frequency divider 11 is a fixed frequency signal oscillated by the fixed frequency oscillator 25. and have the same phase. In addition, if the division ratio N of the frequency divider circuit 12 in the steady state is set to 8, for example, the frequency divided output pulse becomes H when the frequency divider circuit 12 counts 8 O's (including 0 for reset). .

When the frequency division output pulse is output and the phase advance signal is H, the frequency division ratio control circuit 21 sends 9 as the frequency division ratio N to the frequency division circuit 12, and the next operation clock is set to 9. At the rising edge (see point a in FIG. 3), the frequency dividing ratio of the frequency dividing circuit 12 is set to 9. At the same time, the phase advance signal is sent to the AND circuit 23 via the EX-OR circuit 22, and the output of the AND circuit 23 becomes H. At this time, when the operating clock signal is input to the clock terminal, both terminals J and J of the JK flip-flop 24 become H, and the output Q
, Q is inverted. As a result, the phase of the operating clock is inverted in the phase inverting circuit 14 (see the clock at point a in Figure 3), and at the rising edge of the next operating clock, π (rad
) will proceed. Note that the output level of the divide-by-2 circuit 13 is also switched at the rising edge when the phase of the operating clock is inverted.

Since the frequency division ratio N is set to 9, the next frequency division output pulse is output when the 9th count is counted. The actual frequency division ratio up to the timing when the next frequency division ratio is set (point b) is 8.5. The output level of the divide-by-2 circuit 13 is switched at the rising edge of the operation clock at point b.

When the phase delay signal is output, the frequency division ratio control circuit 2
1 outputs 8 as the frequency division ratio N. Then, the phase is reversed by the same operation as when the phase is advanced, and the phase of the operating clock becomes π.
(rad) proceed. In addition, since the frequency division ratio at this time is 8, the frequency division ratio N=
The actual frequency division ratio from when 8 is set until the next frequency division ratio is set is 7.5.

In this embodiment, by operating as described above, the fixed frequency signal input to the frequency divider 11 is 17
The frequency is divided by 15 during frequency division and phase lag, and the frequency is divided by 16 during steady state. In the conventional example, the phase of the output signal is divided by the frequency divider 11.
In this example, control is performed in steps of one period of the fixed frequency signal, but in this embodiment, control is performed in steps of one period of the fixed frequency signal.
It can be controlled in cycles, that is, steps of 2π/16 (rad).

Effects of the Invention Since the digital phase-locked loop circuit of the present invention is configured as detailed above, the phase change step during phase correction can be reduced to 1/1 of the conventional one without changing the frequency of the fixed frequency signal.
It can be reduced to 2. Therefore, the applicable frequency of the digital phase-locked loop circuit can be reduced because the phase change step can be reduced without increasing the fixed frequency oscillator's launch frequency or increasing the operating speed requirements of the frequency divider components. This has the effect of expanding the range.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a diagram of an embodiment of a digital phase-locked loop circuit according to the present invention, Fig. 3 is a timing chart according to the embodiment of Fig. 2, and Fig. 4 is a diagram of a conventional digital phase-locked loop circuit. A circuit diagram of a phase-locked loop circuit, FIG. 5 shows a configuration diagram of a conventional control circuit and a frequency dividing circuit, and FIG. 6 shows a timing chart of a conventional example. 10... Phase comparator, 11... Frequency divider, 12... Frequency divider circuit, 13... Frequency divider circuit, 14... Phase inversion circuit, 15.16.23... AND Circuit, 17.31.32... OR circuit, 18.19... Control circuit, 20... Counting circuit, 21... Frequency division ratio control circuit, 22 ・EX-OR circuit, 24...・JK flip-flop, 25...fixed frequency oscillator, 26...buffer, 27...inverter buffer? , 28.30...k-stage shift register, 29...m-stage shift register. I came from f) Ding Ishitaru Kane@Monkagetsuroof゛匝IW,
Fig. 4 of l's block circle

Claims (1)

[Claims] The phases of the input signal and the output signal are compared by a phase comparator (10), and if the phases between the two are different, a frequency divider (10) is used to compare the phases of the input signal and the output signal.
11), a phase inversion circuit (14) inverts the phase of a fixed frequency signal that is the operating clock of the frequency divider (11), and a frequency divider according to the phase lead or phase lag. (11) and phase inversion circuit (1
A control circuit (18) that sends a control signal to 4) is provided, and the phase change step of the phase correction is set to 1/2 cycle of the fixed frequency signal by inverting the phase of the fixed frequency signal when the phase is advanced or delayed. A digital phase-locked loop circuit characterized by: