JPS6223515B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a vertical synchronization reset pulse forming circuit for PAL and SECAM synchronization signal generators.

In order to synchronize the vertical synchronization signal obtained from the synchronization signal generator with the external vertical synchronization signal, the vertical synchronization signal forming circuit (frequency dividing circuit) is reset (V-reset) based on the external synchronization signal (reference signal). . In this case, for example, in the PAL system, the configuration of the external synchronization signal serving as the reference signal is not single, but there are multiple types, and the configurations can be roughly divided into the following two types.

There is a so-called VBS signal as the first external synchronization signal. This is a composite signal that is the same as a normal color video signal composed of a video signal, a burst signal, and a composite synchronization signal. To form a reset pulse from this composite signal, for example, a composite synchronization signal and a burst flag pulse formed from the composite synchronization signal are used.

Note that the so-called BS signal composed of a burst signal and a composite synchronization signal has no essential difference from the first external synchronization signal.

The second external synchronization signal may be a composite signal consisting of a composite synchronization signal, a line signal (or PAL-pulse), and a color subcarrier signal. In this case as well, a reset pulse is formed based on this composite synchronization signal and line signal.

The reset pulse forming circuit must be constructed so that a reset pulse can always be obtained in a predetermined field at the same timing (same phase) regardless of which of the first and second external synchronization signals is input.

In other words, if the field in which the reset pulse is obtained differs depending on the type of external synchronization signal, or if the timing in which the reset pulse is obtained differs even in the same field, the synchronization signal generation regulated by this reset pulse may be affected. This is because the phase of the vertical synchronizing signal from the external vertical synchronizing signal cannot always be maintained in a fixed phase relationship with the phase of the external vertical synchronizing signal.

Therefore, the present invention proposes a reset pulse forming circuit that can always obtain a reset pulse in the same field at the same timing, regardless of the type of external synchronization signal. The present invention particularly targets synchronization signal generators of the PAL system and the SECAM system.

Next, an example of the present invention will be explained with reference to FIG. 1. This embodiment is a PAL type reset pulse forming circuit, and the external synchronizing signals include the first and second external synchronizing signals described above. think of.

As shown in the figure, the reset pulse forming circuit according to the present invention includes a pulse signal forming circuit 10 synchronized with an external composite synchronizing signal, and a reset pulse forming circuit 10 for forming a reset pulse from the horizontal period and vertical period pulse signals obtained from the pulse signal forming circuit 10. It is composed of a pulse forming circuit 20. A signal based on an external synchronization signal is supplied to the terminals 30a to 30c. That is, terminal 3
0a is supplied with an external composite synchronization signal COP {Fig. 2 _A1 (first field) to _A4 (fourth field)}, and a burst flag pulse BF is supplied to terminal 30b.
(C ₁ to C ₄ in the figure) are supplied, and a line signal ALT (B ₁ to _{B 4} in the figure) is supplied to the terminal 30c.

The burst flag pulse BF is formed, for example, based on the external composite synchronization signal COP and the burst signal as described above.

The pulse signal forming circuit 10 is configured using a plurality of frequency dividing counters. This formation circuit 10
, 1 is a clock pulse P _C forming circuit;
2 is a circuit for forming a horizontal period pulse signal S _H having a predetermined pulse width based on the external composite synchronization signal COP, and 3 is a circuit for forming a vertical period pulse signal S _V from the external composite synchronization signal. This is the circuit.

The clock pulse P _C forming circuit 1 is configured as a PLL. 5 is a VCO whose oscillation frequency is nf _H
(n≧4, f _H is the horizontal synchronization frequency), which is counted down to 1/n by the frequency dividing counter 6, and its output is phase compared with the horizontal period pulse signal S _H as described later. The phase comparison output is supplied to the VCO 5 as its control voltage through the low-pass filter 8, whereby the clock pulse P is locked to the phase of the horizontal synchronization signal P _H of the external composite synchronization signal COP. _C is formed.

As shown in the figure, the circuit 2 for forming the horizontally periodic pulse signal S _H is composed of a counter 11 and an inhibit circuit 12 provided on the reset terminal R side of the counter 11.
COP is supplied. Therefore, this counter 11
is reset by the external composite synchronization signal COP, but if this synchronization signal COP itself is reset, the counter 11 will not be able to obtain the horizontal period pulse signal S _H when the equalization pulse or vertical synchronization pulse is input. When these pulses are input, it must be devised so that it does not respond to pulses every 1/2 horizontal period, but only responds to pulses every 1 horizontal period.

For this purpose, first, the pulse width W ₁ of the first pulse signal S _H obtained from the counter 11 is selected to be greater than or equal to 1/2 horizontal period and less than or equal to 1 horizontal period. Therefore, the counter 11 is selected so that the counting state is stopped and the counter output is inverted when the count number x after the counting state is reset satisfies the expression (2).

1/2<x/n<1 ………(1) ∴n＜2x＜2n ………(2) If the pulse width W ₁ is selected for the 3/4 horizontal period, the formation circuit 1 Clock pulse P by PLL system
The first forming circuit 2 will not malfunction even due to jitter that occurs until the phase of _C is clocked.

Further, in order to prevent the counter 11 from being reset every 1/2 horizontal period, the counter output and the inhibit output of the composite synchronization signal COP are supplied to the counter 11 as a reset pulse. The operation when the composite synchronization signal COP is input will be explained with reference to FIG. However, in the same figure, the signals A _O , B _O ... H _O with the subscript "O" are signals related to odd fields, and the signals with the subscript "E"
The signals _E , B _E . . . H _E are signals related to even fields. And symbols without subscripts D, I, J,
K is a signal common to both fields. Also, numerical subscripts indicate fields.

In an even field, when the horizontal synchronizing pulse P _H is input to the counter 11, the counter 11 is reset and starts counting, and x
When counted up to, the counter output is inverted, so that a pulse signal S _HE with a pulse width W ₁ corresponding to the count number x is obtained. In the equalization pulse section, the counter 11 is reset by the first pulse, but at the next equalization pulse in the 1/2 horizontal cycle, the counter output is "1", so the inhibit output does not change. , is not reset by this equalization pulse. However, since the counter output is "0" at the third equalization pulse (corresponding to the first horizontal period from the first equalization pulse), when this pulse is input, a reset pulse is obtained and the counter 11 is reset. The operation is the same in the period of the vertical synchronization pulse _Pv .

In this way, a pulse signal S _HE (FIG. 3 B E ) synchronized with the horizontal synchronizing pulse P _H included in the composite synchronizing signal COP( _E ) is formed. In an odd field, a pulse signal S _HO shifted by 1/2 horizontal period is obtained as shown by B _O in the figure.

As shown in the figure, the circuit 3 for forming the vertical period pulse signal S _V is composed of a counter 15 and a D-type flip-flop circuit 16, and the counter 15 in this case is reset by all the synchronization signals included in the composite synchronization signal COP. be done as it is done. FIG. 3 Pulses P _CK of C _E and C _O obtained from the counter 15
The pulse width W ₂ of (P _CKE , P _CKO ) is arbitrary as long as it is 1/2 horizontal period or less.

The pulse _PCK is supplied to the flip-flop circuit 16 as a clock pulse, and the D terminal is supplied with a composite synchronization signal COP. Therefore, from this flip-flop circuit 16, a pulse signal S _V with a vertical period as shown in FIG. 2D is obtained regardless of whether it is an odd field or an even field. This pulse signal S _V is obtained in synchronization with the vertical synchronization pulse P _V included in the composite synchronization signal COP of A _E and A _O in the figure.

The pulse forming circuit 20 forms a target reset pulse P _R based on the horizontal period pulse signal S _H and the vertical period pulse signal S _V. First, the shift amount and pulse width are selected as desired.
In order to form the fourth shift pulses Pa to Pd, first and second shift registers 21 and 22 are provided, and the first shift register 21 is a 4-bit shift register 2 made of a D-type flip-flop circuit.
1, a pulse signal S _V is supplied to the D terminal, and an external composite synchronization signal is supplied as a clock pulse.
COP is supplied.

From this first shift register 21, the first shift pulse Pa shifted by 4 bits (F in the same figure)
and the fourth shift pulse Pd shifted by 1 bit.
(E in the same figure) is output. Fourth shift pulse Pd
is further used as a data input of the second shift register 22.

This shift register 22 is a 3-bit shift register made of a D-type flip-flop circuit, and a second shift pulse shifted by 3 bits from this shift register 22 is a 3-bit shift register made of a D-type flip-flop circuit.
Pb (H _E , H _O in the same figure) and a third shift pulse Pc (G _E , G _O in the same figure) shifted by 2 bits are output, and the second shift pulse Pb is supplied with the first external synchronization signal. The first shift pulse Pa and the third shift pulse Pc are used when the second external synchronization signal is supplied. The case will be explained starting from the case where the first external synchronization signal is supplied.

The second shift pulse b inverted by the inverter 23 is supplied to the AND circuit 24 together with the burst flux pulse BF, but the burst flux pulse BF ₁ in the first field is I ₁ in the same figure, and the third shift pulse
The burst flag pulse BF ₃ in the field is shown in the same figure.
Since I ₃ , the inversion pulse bo of the second shift pulse Pbo obtained especially in the odd field (third field) among the second shift pulses Pb
Only when input is input, the AND output P _BF (J in the same figure) is obtained. That is, this AND output P _BF
becomes a field pulse corresponding to a specific field called the third field.

Reference numeral 25 denotes a timing adjustment circuit, which is composed of two-stage flip-flop circuits 25A and 25B, and is configured to switch when the first external synchronization signal is input.
Since SW is switched as shown in the figure, the field pulse _PBF is the RS type flip-flop circuit 2.
Supplied as a 5A reset pulse. A horizontally periodic pulse signal S _HO is supplied as the set pulse, so that an inverted output ₁ shown in FIG.

If a horizontally periodic pulse signal S _HO is used as a clock pulse for the flip-flop circuit 25B, a pulse P _R as shown in the figure L can be obtained over a period of 1H immediately after the inverted output ₁ is obtained. This pulse _PR is used as a reset pulse.

Next, the formation of a reset pulse when a second external synchronization signal is input instead of the first external synchronization signal will be explained with reference to FIG. At this time, the first and third shift pulses Pa and Pc are used.
That is, the AND circuit 30 receives the first shift pulse Pa and the third shift pulse _C whose phase has been inverted.
is supplied. The third shift pulse P _C is G in the same figure.
Since the pulse widths are different as shown by _E and G _O , there is no AND output in even fields (I _E in the same figure),
Only in the case of an odd number field, the AND output Pe of I _O in the figure is obtained. i.e. this AND output
Pe becomes a pulse indicating an odd field.

On the other hand, the line signal ALT ₁ in the first field is J ₁ in the same figure, and the line signal in the third field is
Since ALT ₃ is J ₃ in the figure, if this line signal ALT and AND output Pe are ANDed in the AND circuit 31, the AND output shown in K in the figure at the third field, that is, the field pulse P _ALT is obtained. Since this field pulse _PALT is supplied to the flip-flop circuit 25A through the switch SW, the inverted output ₁ shown in the figure L is obtained as in the case described above, so that the pulse M in the figure, that is, the reset pulse _P'R , is obtained. That's what you get.

Here, both the reset pulse P _R formed when the first external synchronization signal is input, and the reset pulse P' _R formed when the second external synchronization signal is input, are both in the third field. Moreover, since they are obtained at the same timing, the V-reset for the synchronization signal generator can always be reset at the same timing, regardless of the type of external synchronization signal.

That is, although the field pulse P _BF for the first external synchronization signal and the field pulse P _ALT for the second external synchronization signal are obtained at different timings, the timing adjustment circuit 25 adjusts the timing between the two. The timings of the reset pulses P _{R and} P' R are adjusted so that the reset pulses P R and P' _R are always obtained at the same timing.

As explained above, according to the present invention, regardless of the type of external synchronization signal, the reset pulses P _R ,
Since both _P'R 's are obtained in the third field and at the same timing, the vertical synchronization can always be reset at the same timing regardless of the type of external synchronization signal.

In the above embodiment, the present invention is applied to a PAL type reset pulse forming circuit, but it can also be applied to a SECAM type reset pulse forming circuit. In this case, it is sufficient to switch the switch SW to the (2) side and set the input level of the terminal 30c to a high level.

[Brief explanation of the drawing]

FIG. 1 is a system diagram showing an example of the present invention, and FIGS. 2 to 4 are waveform diagrams for explaining its operation. 10 is a forming circuit for pulse signals S _H and S _V ; 20 is a pulse forming circuit for reset pulses P _R and P'_R;
COP is an external composite synchronization signal, BF is a burst flag pulse, ALT is a line signal, 25 is a timing adjustment circuit, 21 and 22 are shift registers, P _BF ,
P _ALT is a field pulse.

Claims (1)

[Claims] 1 A horizontal period pulse signal and a vertical period pulse signal are formed from the external composite synchronization signal, the first to third shift pulses are formed from these pulse signals, and the first to third shift pulses are formed from the first shift pulse and the third shift pulse. A pulse corresponding to an odd field or an even field is formed, a field pulse corresponding to a particular field is formed based on this pulse and an external line signal, and a field pulse corresponding to a particular field is formed based on the second shift pulse and an external burst flag pulse. A field pulse corresponding to the same field as the above field is formed, and one of these field pulses is supplied to a timing adjustment circuit to form a reset pulse in the above specific field at the same timing regardless of the type of external synchronization signal. This is the reset pulse forming circuit.