JPS6152570B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device that operates based on a synchronization signal given from the outside, and is used to uniquely determine the internal state of the semiconductor device when evaluating the functionality of the semiconductor device. The present invention relates to a semiconductor device in which a clear signal is supplied from the same terminal as the synchronization signal.

FIG. 1 is a block diagram showing an example of a semiconductor device that operates based on an externally applied synchronization signal. As shown in the figure, a semiconductor device 1 includes an input section 3 to which an input signal is supplied from the outside via a terminal 2 and converts the input signal into input data, and an operation section 3 that performs various arithmetic operations according to the input data of the input section 3. unit 4, a storage unit 5 for temporarily storing the arithmetic processing result data in this calculation unit 4 and input data in the input unit 3, converting the data stored in this storage unit 5 into a signal and transmitting it to the outside via a terminal 6; It is composed of an output section 7 that outputs an output, and a counting section 9 that is supplied with a synchronization signal from the outside through a terminal 8, sequentially counts the synchronization signal, and supplies drive signals to the input section 3, calculation section 4, and storage section 5, respectively. has been done.

In the conventional semiconductor device shown in FIG. 1 above,
By supplying a synchronization signal to the counting section 9 via the terminal 8, a count clear signal is first generated;
By this count clear signal, the output states of each counter in the counting section 9 are all cleared to zero.
The point at which the clearing is completed becomes a synchronization point, and after this point, the counter 9 sequentially generates drive signals. That is, at present, the count clear signal generated by this counting section 9 is used only for clearing each counter within this counting section 9 or other counters within the semiconductor device 1.

Now, if we consider the function evaluation test of semiconductor devices, in the case of producing small quantities of semiconductor devices with the same function, an evaluation test is performed by applying an input signal and a synchronization signal to each semiconductor device, and outputting the output signal at that time. is detected, and based on this output signal, it is determined whether the semiconductor device is a good product or not. When producing semiconductor devices in small quantities, the above-mentioned test method may be used, but when producing in large quantities, the reliability and manufacturing cost of semiconductor devices are greatly influenced by the evaluation test method and evaluation process. Among the evaluation tests for mass-produced semiconductor devices, one of the most reliable evaluation tests and one in which the evaluation cost accounts for a relatively low proportion of the total manufacturing cost of the semiconductor device is a comparison test. FIG. 2 is a configuration diagram for explaining one example of this comparative test. In FIG. 2, reference _{numeral 11} is a standard semiconductor device whose function has been evaluated in advance and has already been confirmed to be a good product. Reference numeral ₁₂ is a test semiconductor device of the same type as the standard semiconductor device ₁₁ , which is to be subjected to a functional evaluation test. This test semiconductor device 1 ₂ and the standard semiconductor device 1 ₁ are connected to terminals 2 ₂ , 2 ₁ for supplying input signals and terminals 8 ₂ , 8 ₁ for supplying synchronization signals, respectively. Given. Furthermore, the terminals 6 ₁ and 6 ₂ from which both the output signals of the semiconductor devices 1 ₁ and 1 ₂ are output are both supplied to the comparator 11 . This comparator 11 sequentially compares both the output signals of the semiconductor devices 1 ₁ and 1 ₂ and sends the comparison result to the judge 1
2. This determiner 12 determines the quality of the semiconductor device under test ₁₂ according to the comparison result supplied from the comparator 11. At this time, as shown in FIG. 1, if both the semiconductor devices 1 ₁ and 1 ₂ include a memory section 5 consisting of a register or the like, the memory contents of the memory section 5 will remain the same unless new data is supplied. There is no guarantee that it will be. That is, in the functional evaluation test as shown in FIG. 2, there is a strong possibility that the semiconductor device under test ₁₂ will be judged as a defective product even though it is operating normally.

For this reason, conventionally, as shown in FIG. 1, a terminal 10 is used to supply a clear signal to a semiconductor device including a storage section 5 to uniquely determine the contents of this storage section 5, for example, to set the meat volume to 0. are provided and connected as shown in FIG. 3, and before comparing the output signals in a comparison test, clear signals are input to these terminals 10 ₁ and 10 ₂ to clear the contents of the memory section 5. I was trying to set the contents to 0. In other words, the newly provided terminals 10 ₁ and 10 ₂ for supplying clear signals to both semiconductor devices 1 ₁ and 1 ₂ supply input signals necessary for the semiconductor devices 1 ₁ and 1 ₂ to perform their original functions. It is not a terminal, but is provided separately from its function. For this reason, in conventional semiconductor devices, the number of terminals increases by one, which increases the number of bonding points in the assembly process, lowering reliability, and increases the manufacturing cost due to the larger package. It was hot.

The present invention has been made in consideration of the above-mentioned circumstances, and its object is to provide a semiconductor device that operates based on a synchronization signal supplied from the outside and includes a memory circuit, at least one stage for delaying the synchronization signal. A delay circuit is provided, and a gate circuit that obtains an AND of the delayed output signal of this delay circuit and the synchronization signal, and when a signal having a pulse length of a certain pulse width or more is added to the synchronization signal, the gate By obtaining a clear signal in the circuit and uniquely determining the memory contents of the memory circuit by this clear signal,
It is an object of the present invention to provide a semiconductor device that can perform a functional evaluation test without increasing the number of terminals.

An embodiment of the semiconductor device of the present invention will be described below with reference to the drawings. FIG. 4 is a block diagram showing an embodiment of the semiconductor device of the present invention. The semiconductor device 21 includes an input section 23 that is supplied with an input signal from the outside via a terminal 22 and converts the input signal into input data, an arithmetic section 24 that performs various arithmetic processing according to the input data of the input section 23, A storage unit 2 that temporarily stores the calculation result data in the calculation unit 24 and the input data in the input unit 23
5. An output section 27 converts the data stored in the storage section 25 into a signal and outputs it to the outside via a terminal 26. A synchronizing signal is supplied from the outside via the terminal 28, and the above data is synchronized with this synchronizing signal. input section 23,
A counting section 29 consists of a first stage 29a and a second stage 29b that supply drive signals to the calculation section 24 and the storage section 25, respectively.A synchronizing signal is supplied from the outside via the terminal 28, and a pulse width of a certain length or more is detected in this synchronizing signal. For example, when a pulse having a pulse length corresponding to 4 bits or more of clock pulses φ ₁ and φ ₂ to be described later is included, a clear signal is output to the storage section 25 to erase the stored contents. The clear signal generating section 30 is configured to perform a clear signal generating section 30.

FIG. 5 is a detailed configuration diagram of the clear signal generating section 30 that outputs a clear signal to the storage section 25. As shown in FIG. In FIG. 5, three 1-bit shift registers 31-33 are connected in series. A synchronizing signal S is supplied to the input terminal of this first-stage 1-bit shift register 31. Further, the output signal of the 1-bit shift register 33 in the subsequent stage is supplied to an AND gate 34, and the synchronizing signal S is directly supplied to this AND gate 34. Two-phase clock pulses φ ₁ and φ ₂ are supplied to each of the three 1-bit shift registers 31 to 33, and these two-phase clock pulses φ ₁ and φ ₂ cause each of the 1-bit shift registers 31 to 33 to be shifted. is driven. The above three 1-bit shift registers 31 to 3
3 is an n-channel as shown in FIG. 6, for example.
MOS type FET41 ~ Inverter 42 ~ n channel
A 1-bit dynamic shift register connected in series, such as a MOS type FET 43 to an inverter 44, is used. That is, in FIG. 6, an input signal is given to the source (drain) of the n-channel MOS type FET 41, an output signal is obtained from the output terminal of the inverter 44, and then an input signal is applied to the source (drain) of the n-channel MOS type FET 41.
Clock pulses φ ₁ and φ ₂ are applied to gates 41 and 43, respectively.

FIG. 7 shows the first stage 2 of the counting section 29 shown in FIG.
As described above, the first stage 29a generates a count clear signal that clears the output states of the subsequent counters to 0, for example. As shown in the figure, the first stage 29a of the counting section 29 includes a NOR gate 51 to which a synchronizing signal S is supplied, an n-channel MOS type FET 52 to which the output signal of this NOR gate 51 is supplied to the source (drain), and a drain ( an inverter 53 to which the source (source) output signal is supplied; an n-channel MOS type in which the output signal of this inverter 53 is supplied to the source (drain);
It is composed of an FET 54 and an inverter 55 to which the drain (source) output signal of this MOS type FET 54 is supplied. Further, the output signal of the inverter 55 is fed back to the NOR gate 51, and the two n-channel MOS FETs 5
Clock pulses φ ₁ and φ ₂ are supplied to the gates of inverters 2 and 54, respectively.
The output signal of the next stage, that is, the stage 29 after the counting section 29
b.

FIG. 8 is a block diagram when performing a functional evaluation test of the semiconductor device of the present invention shown in _FIG .
is a standard semiconductor device whose functions have been evaluated in advance and have been confirmed to be of good quality.
Reference numeral ₂₁₂ is a test semiconductor device of the same type as the standard semiconductor device ₂₁₁ , on which these functional evaluation tests are performed. Terminals 22 ₂ , 22 1 and terminals 28 _{2 , 28 1 of} this test semiconductor device ₂₁ 2 and the standard semiconductor device 21 ₁ are connected to each other, and an input signal and _a synchronization signal S are respectively applied thereto. Furthermore, both terminals 26 ₁ and 26 ₂ of the semiconductor devices 21 ₁ and 21 ₂ are supplied to the comparator 11. As described above, this comparator 11 sequentially compares both the output signals of the standard semiconductor device 21 ₁ and the test semiconductor device 21 ₂ and supplies the comparison result to the determiner 12 .
Further, the quality of the test semiconductor device 212 is determined according to the comparison result supplied to the determination device ₁₂ from the comparator 11. As shown in FIG. 8, there are a standard semiconductor device 21 ₁ and a test semiconductor device 21 _2.
The case where a function evaluation test is performed by connecting the following will be explained using the time charts shown in FIGS. 9a to 9k. First, in each of the 1-bit shift registers 31 to 33 of the clear signal generating section 30, the signals a and b shown in FIG.
As shown in FIG. 2, two-phase clock pulses φ ₁ and φ ₂ having mutually opposite phases are applied.Next, in order to conduct a functional evaluation test of the semiconductor device under test 21 ₂ , the terminals 22 of both semiconductor devices 21 ₁ and 21 ₂ are applied. Input signals to terminals ₁ , 22 ₂ , and terminals 28 ₁ , 28
₂ , as shown in FIG. 9c, the clock pulse φ ₁ ,
A signal _S1 having a pulse width corresponding to 8 bits of _φ2 is input. At this time, this signal S ₁ consists of three 1s.
1 sequentially by bit shift registers 31 to 33
The signal S1OUT is delayed bit by bit, and as a result, the signal _S1OUT outputted from the 1-bit shift register 33 at the subsequent stage is delayed by 3 bits from the signal _S1 , as shown in FIG. 9d. Next, the AND gate 34 to which the output signal _S1OUT and the signal _S1 of the 1-bit shift register 33 in the latter stage is input corresponds to the length of 5 bits of the clock pulses _φ1 and _φ2 , as shown in FIG. 9e. A clear signal C1 having a pulse width of ₁ is generated and output to the storage section 25. After this, the storage section 25 to which the 5-bit long clear signal _C1 is input clears all of its stored contents by inputting this clear signal _C1 . On the other hand, both semiconductor devices 21 ₁ , 21
A signal S ₂ having a pulse width corresponding to one bit of the clock pulses φ ₁ and φ ₂ is inputted to the terminals 28 ₁ and 28 ₂ of the clock pulses 28 1 and 28 ₂ as shown in FIG. 9 f. At this time, this signal _S2 is sent to three 1-bit shift registers 31.
.about.33, and as a result, the signal _S2OUT outputted from the 1-bit shift register 33 at the subsequent stage is delayed by 3 bits from the signal _S2 , as shown in FIG. 9g. At this time, an AND gate 34 to which the output signal _S2OUT of the 1-bit shift register 33 in the subsequent stage and the signal _S2 are input.
The output signal of does not change (remains low level). That is, no clear signal is generated at this time.
Next, a synchronizing signal S ₃ having a pulse width corresponding to one bit of the clock pulses φ ₁ and φ ₂ is inputted to the terminals 28 ₁ and 28 ₂ as shown in FIG. 9h. At this time, the clear signal generating section 30 does not generate a clear signal as described above. One terminal 28 ₁ , 28
The synchronizing signal S ₃ input to the counter ₂ is input to the first stage 29 a of the counting section 29 . By inputting the synchronizing signal _S3 , at _T1 , the output signal _G3 of the inverter 55 is synchronized with the synchronizing signal S3 so that two bits are initially set to ₀ as shown in FIG. 9k. Thereafter, the output signal _G3 of this inverter 55 is sequentially inputted to the subsequent stage 29b of the counting section 29. Note that FIG. 9 ii shows the output signal G ₁ of the NOR gate 51, and FIG. 9 j shows the output signal G ₂ of the inverter 53. In this way, by inputting a pulse having a sufficiently longer pulse width than the synchronizing signal (here, 7 bits or more) to the terminal for supplying the synchronizing signal, the memory contents of the memory section 25 can be cleared to 0, and then the functional evaluation test can be performed reliably. becomes possible.

The present invention is not limited to the one embodiment described above; for example, in the above embodiment, the number of successive stages of the 1-bit shift register in the clear signal generating section 30 is three, and a 3-bit delay circuit is configured. However, it goes without saying that any number of 1-bit shift registers may be used.
Further, in the above embodiment, a case has been described in which a pulse width of 4 bits or more is required as a clear signal for clearing the contents of the memory circuit 25, but it is of course possible to use any number of bits.

As explained above, according to the present invention, in a semiconductor device that operates based on a synchronization signal supplied from the outside and includes a memory circuit, the semiconductor device includes at least one stage of delay circuit for delaying the synchronization signal, and a delay circuit for delaying the synchronization signal. A gate circuit is provided to obtain a logical product of the delayed output signal and the synchronization signal, and when a signal having a pulse length longer than a certain pulse width is added to the same basic signal, the gate circuit obtains a clear signal. By uniquely determining the memory contents of the memory circuit using the clear signal, it is possible to provide a semiconductor device that can reliably perform a functional evaluation test without increasing the number of terminals.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing a conventional semiconductor device.
FIGS. 2 and 3 are block diagrams when performing a function evaluation test of a conventional semiconductor device, respectively. FIG. 4 is a block diagram showing an embodiment of the semiconductor device of the present invention, and FIG. 5 is a block diagram based on the above embodiment. 6 is a block diagram showing an example of a 1-bit shift register used in the clear signal generating section, and FIG. 7 is a block diagram showing the first stage of the counting section 29 from the above embodiment. 29a is extracted and shown in detail, FIG. 8 is a configuration diagram when performing a functional evaluation test of a semiconductor device according to the present invention, and FIGS. 9 a to 9 k are diagrams for explaining a functional evaluation test of a semiconductor device according to the present invention. It is a time chart. 21 ... semiconductor device, 22, 22 ₁ , 22 ₂ ,
26, 26 ₁ , 26 ₂ , 28, 28 ₁ , 28 ₂ ...
... terminal, 23 ... input section, 24 ... calculation section, 25
... Storage section, 27 ... Output section, 29 ... Counting section,
29a... First stage of counting section, 29b... Second stage of counting section,
30... Clear signal generation section, 31-33... 1-bit shift register, 34... AND gate, 4
1, 43, 52, 54...n channel MOS type
FET, 42, 44, 53, 55...Inverter, 51...Nor gate, 21 ₁ ...Standard semiconductor device, 21a...Semiconductor device under test, 11...Comparator, 12...Determiner.

Claims (1)

[Claims] 1. In a semiconductor device that operates based on clock pulses supplied from the outside and includes a memory circuit inside, a clock pulse with a constant pulse width is supplied from the outside during normal operation or functional testing, and when clearing the memory circuit, A terminal to which a synchronizing signal whose pulse width is set longer than the clock pulse is supplied, at least one stage of delay circuit for delaying the synchronizing signal supplied to the terminal, and a connection between the output signal of the delay circuit and the synchronizing signal. 1. A semiconductor device comprising: a clear signal generation circuit comprising a gate circuit that generates a clear signal for the storage circuit by performing a logical product.