JPH0683583A - Pipeline arithmetic operation circuit - Google Patents

Abstract

PURPOSE:To improve the processing speed when the clock speed is low. CONSTITUTION:When the clock speed is high, a select generating circuit 18 generates a select signal whose level is low and when the clock speed is low, the select generating circuit 18 generates a select signal whose level is high. When the select signal is at an L level, a selector 14 connects an output from a latch circuit 12-2 to the position of an arithmetic operation circuit 10-B so that the latch circuit 12-2 is interposed between the arithmetic operation circuits 10-A, 10-B. When the select signal is at an H level, while the latch circuit 12-2 is reset, the selector 14 connects the output of the arithmetic operation circuit 10-A to the position of the arithmetic operation circuit 10-B, then the latch circuit 12-2 is in the through-state. When the clock speed is low and the arithmetic operation by both the arithmetic operation circuits 10-A, 10-B is finished within one period, the latch circuit 12-2 is automatically set to the through-state and then the processing speed is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pipeline arithmetic circuit configured as a semiconductor integrated circuit or the like.

[0002]

2. Description of the Related Art Generally, asynchronous arithmetic circuits (combinational circuits)
When an arithmetic circuit is constructed by using the above, the circuits are constructed in a pipeline manner by interposing a latch circuit, a flip-flop, etc. between each arithmetic circuit. FIG. 7 shows the configuration of a pipeline arithmetic circuit according to a conventional example.

The circuit shown in this figure includes two arithmetic circuits 10-A and 10-B and three latch circuits 12-1 to 12-1.
12-3. Input data to the circuit shown in this figure is latched by the latch circuit 12-1 in accordance with a clock of a predetermined frequency and input to the arithmetic circuit 10-A. The arithmetic circuit 10-A performs predetermined arithmetic processing (hereinafter, referred to as “input data” input via the latch circuit 12-1).
(Denoted as "A") and outputs the result. Latch circuit 12-2 provided in the subsequent stage of the arithmetic circuit 10-A
Latches the calculation result of the calculation circuit 10-A according to the clock, and the calculation circuit 10-B performs a predetermined calculation process (hereinafter referred to as “B”) on the data latched by the latch circuit 12-2. Give. The calculation result of the calculation circuit 10-B is latched by the latch circuit 12-3 according to the clock. In the figure, latch circuits 12-1 to 12-3
Are reset when the reset signal is H.

[0004]

However, in the pipeline arithmetic circuit having such a configuration, there is a problem that the pipeline operation becomes a bottleneck of the processing speed especially when the clock frequency is low. . For example, in the circuit shown in FIG. 7, the clock frequency is usually determined according to the data rate of the input, and when the data rate is low, the clock frequency is also set low. Clock cycle is T, arithmetic circuit 1
Processing the 0-A the time required for the "A" T _A, when the time required for arithmetic processing "B" in the arithmetic circuit 10-B was T _B, the lower the clock frequency, holds the following relationship .

T> T _A + T _B When such a relationship is established, one clock cycle T
Even though the arithmetic processings "A" and "B" can both be completed in the above, 2T is required for the processing.

The present invention has been made to solve the above problems, and an object thereof is to speed up the operation when the clock frequency is low.

[0007]

In order to achieve such an object, the pipeline arithmetic circuit of the present invention latches the arithmetic circuit of the arithmetic circuit of the previous stage when the arithmetic circuit of the arithmetic circuit of the preceding stage is supplied to the arithmetic circuit of the latter stage. It is characterized in that a switching means for switching whether or not the circuit is interposed is provided.

Further, the pipeline arithmetic circuit of the present invention is
The switching means includes a means for detecting the clock speed and a means for giving a signal to the switching means to intervene the latch circuit when the detected clock speed is high and not intervening when the detected clock speed is low. The switching is performed according to the signal.

[0009]

In the pipeline arithmetic circuit of the present invention, it can be switched whether the latch circuit is interposed between the arithmetic circuits of the preceding and succeeding stages. When interposing a latch circuit,
The calculation result of the arithmetic circuit of the preceding stage is once latched by this latch circuit and then supplied to the arithmetic circuit of the succeeding stage.
When the latch circuit is not interposed, the arithmetic circuit in the previous stage is not latched by the latch circuit and is supplied to the arithmetic circuit in the subsequent stage. Therefore, by appropriately performing this switching, it is possible to switch the circuit configuration to a pipeline type configuration or a part thereof to a latch through configuration.

By performing this switching according to the clock speed, the processing speed can be improved especially when the clock speed is low. That is, when the clock speed is low, the switching is performed by externally applying a select signal or the like to the switching means, or the clock speed is detected as in claim 2, and the switching is automatically performed based on the detection result. By doing so, the processing speed when the clock speed is low is improved.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings. It should be noted that the same components as those of the conventional example shown in FIG.

FIG. 1 shows the configuration of a pipeline arithmetic circuit according to the first embodiment of the present invention. The circuit shown in this figure has a configuration in which a selector 14 and an OR gate 16 are further added to the circuit of the conventional example shown in FIG. The selector 14 outputs the output of the arithmetic circuit 10-A when the select, which is a signal supplied from the outside, is H.
0-B, and when L, the output of the latch circuit 12-2 is connected to the arithmetic circuit 10-B. The OR gate 16 is
A gate for resetting the latch circuit 12-2,
Its inputs are both reset and select signals.

Therefore, the operation of the pipeline arithmetic circuit according to this embodiment is the same as the conventional example when the value of the select signal supplied from the outside is L, and when it is H, the latch circuit 12- Latch through operation is performed by passing through 2. Specifically, when the select signal is L, the output of the arithmetic circuit 10-A is latched by the latch circuit 12-2. Since the select signal has the L value, the selector 14 connects the output of the latch circuit 12-2 to the arithmetic circuit 10-B. Therefore, in this case, the operation is similar to that of the conventional example.
Conversely, when the select signal has the H value, the latch circuit 12-2 is reset, while the selector 14 connects the output of the arithmetic circuit 10-A to the arithmetic circuit 10-B. Therefore, in this case, the latch circuit 12-2 does not intervene between the arithmetic circuits 10-A and 10-B.

The select signal used in this embodiment has an L value when the input data rate is high and therefore the clock frequency is set high, and conversely H when the clock frequency is set low. Value, set for each. In this embodiment, such a setting can improve the processing speed especially when the clock frequency is low. This principle is shown in FIG.

First, as shown in FIG. 2A, when the clock frequency is relatively high, T _A , T _B <T <T _A + T _B
When is satisfied, the select signal is set to the L value. Therefore, similarly to the conventional example, each latch circuit 12-1
Complete pipeline operations through ~ 12-3 are performed.

Next, when the clock frequency is low, T> T _A + T
_{When B} is established, the latch circuit 12-2 is in the through state as shown in FIG. 2 (b2). In this case, in one cycle T of the clock, the arithmetic circuit 10-A
And 10-B, the arithmetic processing "A" and "B" are applied to the input data. Therefore, in this embodiment,
As is apparent from a comparison with the operation of the conventional example shown in FIG. 2B1, the operation result related to the output is 1 clock cycle T.
It will be obtained as soon as possible. As described above, according to this embodiment, a pipeline arithmetic circuit having an improved processing speed can be obtained especially when the clock frequency is low.

FIG. 3 shows the configuration of the pipeline arithmetic circuit according to the second embodiment of the present invention. The circuit shown in this figure has a configuration in which a select signal is generated by an internally provided select generation circuit 18 instead of being input from the outside. The select generation circuit 18 is
The determination regarding the clock frequency is performed, and when the clock frequency is high, an L value select signal is generated, and when the clock frequency is low, an H value select signal is generated.

FIG. 4 shows an example configuration of the select generation circuit 18. The circuit shown in this figure has a series circuit of a resistor R and a capacitor C. Capacitor C
Has one end connected to the power supply and one end of the resistor R grounded. Further, a transistor Tr whose gate is input with a clock is connected in parallel with the capacitor C, and a connection point between the capacitor C and the resistor R is connected to one input end of the flip-flop 20. A clock is input to the other input terminal of the flip-flop 20.

When a clock is supplied to the circuit shown in this figure, the charging / discharging of the capacitor C is executed in synchronization with the clock. That is, when the transistor Tr is turned on, the capacitor C is discharged through the transistor Tr, and then the capacitor C is charged with the time constant CR. Therefore, the potential at the connection point between the capacitor C and the resistor R is shown in FIG.
Alternatively, as shown in (b), a charging / discharging waveform synchronized with the clock is drawn.

When the clock frequency is high, the next discharge is executed while the capacitor C is not sufficiently charged. Therefore, the potential at the connection point between the capacitor C and the resistor R is the flip-flop 20. The threshold V _th related to the input is not exceeded, and therefore the input level to the flip-flop 20 is always the H value. On the contrary, when the clock frequency is low, the charge of the capacitor C is sufficiently advanced until the next discharge, so that the potential at the connection point of the capacitor C and the resistor R is the threshold V related to the input of the flip-flop 20.
becomes the crosses the _th, thus the input level to the flip-flop 20 becomes the L level at some point. At this time, the output level of the flip-flop 20 becomes the H value, and this is used as a select signal and supplied to the selector 14 and the OR gate 16 so that the complete pipeline operation or the latch is performed depending on whether the clock frequency is high or low. It is possible to automatically switch the through operation. FIG. 6 shows the configuration of the pipeline arithmetic circuit according to the third embodiment of the present invention. In this embodiment, the preceding arithmetic circuit 10-A is divided into two arithmetic circuits 10-A1 and 10-A2, and the latch circuit 12-
1 is separated into 12-11 to 12-14, and the latch circuit 12
-2 is separated into 12-21 and 12-22, and the selector 14
And two OR gates 16 (14-1 and 14-2 and 1
6-1 and 16-2) are provided examples.

Even in such a configuration, it is possible to switch between the complete pipeline operation and the latch through operation. The circuit configuration as in this embodiment can be used, for example, in a circuit that performs multiplication of 16 bits × 16 bits, when the multiplication circuit is separately configured into a multiplication circuit of 4 bits × 4 bits.

Further, the present invention does not require any limitation on the contents of the arithmetic processing of each arithmetic circuit 10. For example, in the first or second embodiment, the arithmetic circuit 10-A in the preceding stage is used as a divider circuit, and the quotient and the remainder obtained by the arithmetic circuit 10-A are selectively output by the arithmetic circuit 10-B (selector) in the succeeding stage. Can also be applied to. In this case, it is preferable to provide two latch circuits 12-2 in front of the arithmetic circuit 10-B, a circuit for latching the quotient and a circuit for latching the remainder. Further, in the above description, the circuit configuration by RC charging / discharging is shown as the select generation circuit 18, but the present invention does not need to limit the configuration of this circuit.

[0023]

As described above, according to the pipeline arithmetic circuit of the present invention, when the arithmetic result of the arithmetic circuit of the preceding stage is supplied to the arithmetic circuit of the succeeding stage, the latch circuit is not interposed therebetween. By switching between the two, it is possible to improve the processing speed by passing the latch circuit through when the clock speed is low, for example.

Further, according to the present invention, the clock speed is detected, and it is switched whether the latch circuit is interposed or not according to the detection result. Therefore, the above switching according to the clock speed is automatically performed. It becomes possible.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a pipeline arithmetic circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing an operation of this embodiment in comparison with a conventional example, and FIG. 2 (a) shows a complete pipeline operation executed when a clock frequency is high.
FIG. 2B shows the operation when the clock frequency is low. In particular, FIG. 2B1 shows the complete pipeline operation in the conventional example, and FIG. 2B2 shows the latch-through operation in the embodiment. .

FIG. 3 is a block diagram showing a configuration of a pipeline arithmetic circuit according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing an example configuration of a select generation circuit in this embodiment.

5 is a diagram showing an operation of the select generation circuit shown in FIG. 4, and FIG. 5 (a) shows a case where a clock frequency is high,
FIG. 5B is a diagram showing a voltage waveform at the connection point between the capacitor and the resistor when the clock frequency is low.

FIG. 6 is a block diagram showing a configuration of a pipeline arithmetic circuit according to a third embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a pipeline arithmetic circuit according to a conventional example.

[Explanation of symbols]

10-A, 10-A1, 10-A2, 10-B Arithmetic circuit 12-1, 12-11 to 12-14, 12-2, 12-
21, 12-22, 12-3 Latch circuit 14, 14-1, 14-2 Selector 16, 16-1, 16-2 OR gate 18 Select generation circuit 20 Flip-flop Tr transistor C capacitor R resistance V _{th of} flip-flop Input threshold

Claims (2)

[Claims] 1. A pipe in which a plurality of asynchronous arithmetic circuits are generally cascaded via a latch circuit, and a latch circuit latches an arithmetic result of an arithmetic circuit of a preceding stage to be supplied to an arithmetic circuit of a subsequent stage according to a clock. In the line arithmetic circuit, when supplying the arithmetic result of the arithmetic circuit of the previous stage to the arithmetic circuit of the subsequent stage, a pipeline arithmetic circuit is provided with a switching means for switching whether a latch circuit is interposed between them or not. . 2. The pipeline arithmetic circuit according to claim 1, wherein: means for detecting a clock speed; and a latch circuit intervening when the detected clock speed is high, and not intervening when the clock speed is low. Signal
A pipeline arithmetic circuit, characterized in that the switching means performs the switching in response to the signal.